LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 40

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

The gain can be varied from −0.9375 • GIN to +0.9375 • GIN in 31 steps of 0.0625 • GIN. The AISN gain is determined by the
following equation:
where AISN
There are two special cases to the formula for h
of AISN = 10000 is a special case where the AISN circuitry is disabled and VOUT is connected internally to VIN after the input
attenuator with a gain of 0 dB. This allows a Full Digital Loopback state where an input digital PCM signal is completely processed
through the receive section, looped back, processed through the transmit section, and output as digital PCM data. During this
test, the VIN input is ignored and the VOUT output is connected to VREF.
Speech Coding
The A/D and D/A conversion follows either the A-law or the µ-law standard as defined in ITU-T Recommendation G.711. A-law
or µ-law operation is programmed using MPI Command 60/61h or GCI Command SOP 7. Alternate bit inversion is performed as
part of the A-law coding. In PCM/MPI mode, the QLSLAC device provides linear code as an option on both the transmit and
receive sides of the device. Linear code is selected using MPI Command 60/61h. Two successive time slots are required for linear
code operation. The linear code is a 16-bit two’s-complement number which appears sign bit first on the PCM highway. Linear
code occupies two time slots.
Double PCLK (DPCK) Operation (PCM/MPI Mode)
The Double PCLK Operation allows the PCM clock (PCLK) signal to be clocked at a rate of twice that of the PCM data. This mode
provides compatibility of the QLSLAC device with other existing system architectures, such as a GCI interface system in terminal
mode operating at a 768 kHz data rate with a 1.536 MHz clock rate.
The operation is enabled by setting the DPCK bit of Command C8/C9h. When set to zero, operation is unchanged from normal
PCM clocking and the PCM data and clock rates are the same. When the bit is set to 1, clocking of PCM data is divided by two
and occurs at one half of the PCLK PCM clock rate. The internal PLL used for synchronization of the master DSP clock (MCLK)
receives its input from either the MCLK or PCLK pin, depending on the clock mode (CMODE) selection. If PCLK is used for MCLK
(CMODE = 1), then the clock input is routed to both the DSP clock input and to the time slot assigner. The timing division related
to the double PCLK mode occurs only within the time slot assigner, and therefore, double PCLK operation is available with either
CMODE setting. This allows the MCLK/E1 pin to be available for E1 multiplexing operation if both double PCLK and E1
multiplexing modes are simultaneously required.
Specifications for Double PCLK Operation are shown in the Switching Characteristics section on
Signaling on the PCM Highway (PCM/MPI Mode)
If the SMODE bit is set in the Configuration register (MPI Command 46/47h), each data point occupies two consecutive time
slots. The first time slot contains A-law or µ-law data and the second time slot contains the following information:
Bit 7 of the signaling byte appears immediately after bit 0 of the data byte. A-law or
in order to put signaling information on the PCM highway. The signaling time slot remains active, even when the channel is
inactive.
Robbed-Bit Signaling Compatibility (PCM/MPI Mode)
The QLSLAC device supports robbed bit signaling compatibility. Robbed bit signaling allows periodic use of the least significant
bit (LSB) of the receive path PCM data to be used to carry signaling information. In this scheme, separate circuitry within the line
card or system intercepts this bit out of the PCM data stream and uses this bit to control signaling functions within the system.
The QLSLAC device does not perform any processing of any of the robbed bits during this operation; it simply allows for the
robbed bit presence by performing the LSB substitution.
If the RBE bit is set in the Channel Enable and Operating Mode register (MPI Command 4A/4Bh), then the robbed-bit signaling
compatibility mode is enabled. Robbed-bit signaling is only available in the µ-law companding mode of the device. Also, only the
Bit 7:
Bit 6:
Bits 5–3:
Bit 2:
Bits 1–0:
i
= 0 or 1
Debounced CD1 bit (usually hook switch)
CD2 bit or CD1B bit
Reserved
CFAIL
Reserved
h
AISN
=
AISN
0.0625 GIN
Zarlink Semiconductor Inc.
: 1) a value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value
•
40




i
∑
=
4
0
AISN
i
•
2
i




–
16
µ
-law Companded mode must be specified
page
21.