LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 22

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Master Clock
(See Figure 16 for the Master Clock timing diagram.)
Auxiliary Output Clocks
Notes:
1.
2.
3.
4.
5.
6.
7.
If CFAIL = 1 (Command 55h), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or
switching them to default coefficients; otherwise, a chip select off time of 25 µs is required.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192
MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128
kHz in Companded state and 256 kHz in Linear state, PCM Signaling state, or double PCLK state. The minimum PCM clock rates should
be doubled for parts with only one PCM highway in order to allow simultaneous access to all four channels.
TSC is delayed from FS by a typical value of N • t
t
PCLK and MCLK are required to be integer multiples of the frame sync (FS) frequency. Frame sync is expected to be an accurate 8 kHz
pulse train. If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
Phase jumps of 81 nS will be present when the master clock frequency is a multiple of 1.544 MHz.
TSO
is defined as the time at which the output achieves the Open Circuit state.
No.
37
38
39
40
41
42A
No.
42
43
44
Symbol
J
t
t
t
t
MCR
MCF
MCH
MCY
MCL
Symbol
DC
f
CHP
f
t
E1
E1
CHP
Master clock jitter
Rise time of clock
Fall time of clock
MCLK HIGH pulse width
MCLK LOW pulse width
Chopper clock frequencyCHP = 0
Chopper click duty cycle
E1 output frequency (CMODE = EE1 = 1)
E1 pulse width (CMODE = EE1 = 1)
CHP = 1
Parameter
PCY
Parameter
, where N is the value stored in the time/clock-slot register.
Zarlink Semiconductor Inc.
22
Min
48
48
Min
Typ
292.57
4.923
31.25
Typ
256
50
Max
Max
50
15
15
Unit
kHz
kHz
µs
%
Unit
ns
Notes
Notes
7
7
7
7
6