LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 62

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

GCI Format and Command Structure
The GCI interface provides communication of both control and voice data between the GCI highway and subscriber line circuits
over a single pair of pins on the QLSLAC device. A complete GCI frame is sent upstream on the DU pin and received downstream
on the DD pin every 125 µs. Each frame consists of eight 4 byte GCI channels (CHN0 to 7) that contain voice and control
information for eight pairs of channels. A particular channel pair is identified by its position within the frame (see Figure 26).
Therefore, a total of 16 voice channels can be uniquely addressed each frame. The overall structure of the GCI frame is shown
in Figure 26.
The 4 byte GCI channel contains the following:
n
Signaling and Control (SC) Channel
The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the QLSLAC
device in the C/I field. This allows the upstream processor to have immediate access to the output (downstream) and input
(upstream) data present on the QLSLAC device’s programmable I/O port.
The MR and MX bits are used for handshaking during data exchanges on the monitor channel.
Downstream C/I Channel
The QLSLAC device receives the MSBs first.
The downstream C/I channel SC octet definition depends on the device package type. The 44-pin package does not have
provisions for pin connections to accommodate all SLIC device outputs, which otherwise are available on the higher pin count
devices. For the 44-pin package device, the downstream SC octet is defined as:
<---------------- Downstream SC Octet ------------------>
|<------------------- C/I Field ------------------->|
MSB
7
A
2 bytes; B1 and B2 for voice channels 1 and 2.
One Monitor (M) byte for reading/writing control data/coefficients to the QLSLAC device for both channels.
One Signaling and Control (SC) byte containing a 6-bit Command/Indicate (C/I) channel for control information and
a 2-bit field with Monitor Receive and Monitor Transmit (MR, MX) bits for handshaking functions for both channels.
All principal signaling (real-time critical) information is carried on the C/I channel. The QLSLAC device utilizes the
full C/I channel capacity of the GCI channel.
DU, DD
FS
C5
6
x
C4
5
x
CHN0
0−3
C3
4
B1
x
8
0
CD2
CHN1
3
x
4−7
Figure 26. Multiplexed GCI Time Slot Structure
CD1
2
x
CHN2
8−11
MR
B2
8
1
1
Zarlink Semiconductor Inc.
LSB
MX
0
CHN3
12−15
62
C/I
6
M
8
2
CHN4
16−19
CHN5
20−23
MR
1
SC
8
3
M
CHN6
1
24−27
CHN7
28−31