LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 60

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

E8/E9h Write/Read Ground Key Filter
Filter Ground Key
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the Real Time Data register
described earlier. A value of 0 disables the Ground Key filter for that particular channel.
Power Up and Hardware Reset (RST) Value = x0h.
RSVD
GENERAL CIRCUIT INTERFACE (GCI) SPECIFICATIONS
GCI General Description
When the CS/PG device pin is connected to DGND and DCLK/S0 is static (not toggling), GCI operation is selected. The QLSLAC
device conforms to the GCI standard where data for eight GCI channels are combined into one serial bit stream. A GCI channel
contains the control and voice data for two analog channels of the QLSLAC device. Two GCI channels are required to access all
four channels of the QLSLAC device. The QLSLAC device sends Data Upstream out of the DU pin and receives Downstream
Data on the DD pin. Data clock rate and frame synchronization information goes to the QLSLAC device on the DCL (Data Clock)
and FSC input pins, respectively. Two of eight GCI channels are selected by connecting the S0 and S1 channel selection pins
on the QLSLAC device to DGND or VCCD as shown in Table
In the time slot control block (shown in Figure 25), the Frame Sync (FSC) pulse identifies the beginning of the Transmit and
Receive frames and all GCI channels are referenced to it. Voice (B1 and B2), C/I, and monitor data are sent to the Upstream
Multiplexer where they are combined and serially shifted out of the DU pin during the selected GCI Channels. The Downstream
Demultiplexer uses the same channel control block information to demultiplex the incoming GCI channels into separate voice
(B1 and B2), C/I, and monitor data bytes.
The QLSLAC device supports an eight GCI channel bus (16 analog channels). The external clock applied to the DCL pin is either
2.048 MHz or 4.096 MHz. The QLSLAC device determines the incoming clock frequency and adjusts internal timing automatically
to accommodate single or double clock rates.
DGND
DGND
VCCD
VCCD
S1
Table 8. GCI Channel Assignment Codes
Command
I/O Data
MPI Command
R/W = 0: Write
R/W = 1: Read
GK = 0–15
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
DGND
DGND
VCCD
VCCD
S0
Filter sampling period in 1 ms
GCI Channels #
RSVD
0 & 1
2 & 3
4 & 5
6 & 7
D
1
7
Zarlink Semiconductor Inc.
RSVD
D
1
6
Table
60
RSVD
D
1
5
8.
RSVD
D
0
4
GK3
D
1
3
GK2
D
0
2
GK1
D
0
1
GK0
R/W
D
0