LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 32

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

E1 Multiplex Operation
The QLSLAC device can multiplex input data from the CD1 SLIC device I/O pin into two separate status bits per channel (CD1
and CD1B bits in the SLIC device Input/Output register, MPI Command 52/53h, GCI Command SOP 10 and CDA and CDB bits
in the Real Time Data register, MPI Command 4D/4Fh, GCI Command SOP 13, GCI C/I Channel) using the E1 multiplex mode.
This multiplex mode provides the means to accommodate dual detect states when connected to an Legerity SLIC device, which
also supports ground-key detection in addition to loop detect. Legerity SLIC devices that support ground-key detect use their E1
pin as an input to switch the SLIC device’s single detector (DET) output between internal loop detect or ground-key detect
comparators. Using the E1 multiplex mode, a single QLSLAC device can monitor both loop detect and ground-key detect states
of all four connected SLIC devices without additional hardware. Although normally used for ground key detect, this multiplex
function can also be used for monitoring other signal states.
The E1 multiplex mode is selected by setting the EE1 bit (bit 7, MPI Command C8/C9h, GCI Command SOP 11) and CMODE
bit (bit 4, Command 46/47h) in the QLSLAC device. In PCM/MPI mode, the CMODE bit must be selected (CMODE = 1) for the
master clock to be derived from PCLK so that the MCLK/E1 pin can be used as an output for the E1 signal. The multiplex mode
is then turned on by setting the EE1 bit. With the E1 multiplex mode enabled, the QLSLAC device generates the E1 output signal.
This signal is a 31.25
programmed as an input and should be connected to ground if it is not connected to a clock source. The polarity of this E1 output
is selected by the E1P bit (bit 6, MPI Command C8/C9h, GCI Command SOP 11) allowing this multiplex mode to accommodate
all SLIC devices regardless of their E1 high/low logic definition.
Figure 20 shows the SLIC device Input/Output register, I/O pins, E1 multiplex hardware operation for one QLSLAC device
channel. It also shows the operation of the Real Time Register. The QLSLAC device E1 output signal connects directly to the E1
inputs of all four connected SLIC devices and is used by those SLIC devices to select an internal comparator to route to the SLIC
device’s DET output. This E1 signal is also used internally by the QLSLAC device for controlling the multiplex operation and
timing.
The CD1 and CD1B bits of the SLIC device Input/Output register are isolated from the CD1 pin by transparent latches. When the
E1 pulse is off, the CD1 pin data is routed directly to the CD1 bit of the SLIC device I/O register and changes to the CD1B bit of
that register are disabled by its own latch. When E1 pulses on, the CD1 latch holds the last CD1 state in its register. At the same
time, the CD1B latch is enabled, which allows CD1 pin data to be routed directly to the CD1B bit. Therefore, during this
multiplexing, the CD1 bit always has loop-detect status and the CD1B bit always has ground-key detect status.
This multiplexing state changes almost instantaneously within the QLSLAC device but the SLIC device may require a slightly
longer time period to respond to this detect state change before its DET output settles and becomes valid. To accommodate this
µ
s (1/32 kHz) duration pulse occurring at a 4.923 kHz (64 kHz/13) rate. If EE1 is reset, MCLK/E1 is
Figure 19. Clock Mode Options (PCM/MPI Mode)
Notes:
1. CMODE = Command 46/47h
2. CSEL = Command 46/47h
3. EE1 = Command C8/C9h
4. E1P = Command C8/C9h
Assigner
Engine
Time
Slot
Pulses
DSP
E1P
E1
Zarlink Semiconductor Inc.
CMODE
÷
N
32
(= 1)
CSEL
PCLK
Bit 4
Bits 0–3
Bit 7
Bit 6
(= 0)
(= 0)
MCLK/E1
(= 1)
(= 1)
(= 0)
EE1
E1