LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 30

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

OPERATING THE QLSLAC DEVICE
The following sections describe the operation of the four independent channels of the QLSLAC device. The description is valid
for channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example, VOUT refers to either VOUT
VOUT
Power-Up Sequence
The recommended QLSLAC device power-up sequence is to apply:
1.
2.
3.
The software initialization should then include:
1.
2.
3.
4.
If the power supply (VCCD) falls below an internal threshold, the device is reset and will require complete reprogramming with
the above sequence. A reset may be initiated by connection of a logic Low to the RST pin, or if chip select (CS) is held low for
16 rising edges of DCLK, a hardware reset is generated when CS returns high. The RST pin may be tied to VCCD if it is not used
in the system.
PCM and GCI State Selection
The Le58QL061/063 QLSLAC device can switch between PCM/MPI and GCI modes. Table
requirements.
Analog and digital ground
VCC, signal connections, and Low on RST
High on RST
Wait 1 ms.
For PCM/MPI mode, select master clock frequency and source (Command 46/47h). This should turn off the CFAIL bit
(Command 55h) within 400 µs.
In GCI mode, DCL is the clock source. The CFAIL bit (GCI Command SOP 8) is set to 1 until the device has determined and
synchronized to the DCL frequency, 4.096 MHz or 2.048 MHz. If channels are activated while CFAIL is a 1, no device
damage will occur, but high audible noise may appear on the line. Also, the CD1, CD2, and C3 - C7 bits may not be stable.
Program filter coefficients and other parameters as required.
Activate (MPI Command 0Eh, GCI Command SOP 4).
2
, VOUT
3
, or VOUT
4
.
Power On or
Hardware
Reset
Power On or
Hardware
Reset
GCI
PCM
PCM
GCI
From State
Table 3. PCM/GCI Mode Selection
Zarlink Semiconductor Inc.
PCM
GCI
PCM
GCI
Power On or
Hardware
Reset
Power On or
Hardware
Reset
To State
30
CS = 1 or DCLK has ac
clock present
CS = 0 and DCLK does not
have ac clock present
CS = 1 or DCLK has ac
clock present
No commands yet sent in
PCM state and CS = 0 (for
more than 2 FS) and DCLK
does not have ac clock
present
Commands have been sent
in PCM state and Hardware
Reset generated
Not allowed
Requirement
Table 3
lists the selection
1
,