LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 45

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

MPI COMMAND STRUCTURE
This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow.
For details of the filter coefficients of the form Cxymxy, refer to the General Description of CSD Coefficients section
Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.
*Default field values are marked by an asterisk. A hardware reset forces the default values.
00h Deactivate (Standby State)
In the Deactivate (Standby) state:
02h Software Reset
The action of this command is identical to that of the RST pin except that it only operates on the channels selected by the
Channel Enable Register and it does not change clock slots, time slots, PCM highways, ground key sampling interval
or global chip parameters. See the note under the hardware reset command that follows.
04h Hardware Reset
Hardware reset is equivalent to pulling the RST on the device Low. This command does not depend on the state of the Channel
Enable Register.
Note:
The action of a hardware reset is described in Reset States on
06h No Operation
0Eh Activate Channel (Operational State)
This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until after the
second FS pulse is received following the execution of the Activate command.
Command
Command
Command
Command
Command
MPI Command
MPI Command
MPI Command
MPI Command
MPI Command
All programmed information is retained.
The Microprocessor Interface (MPI) remains active.
The PCM inputs are disabled and the PCM outputs are high impedance unless signaling on the PCM high
way is programmed (SMODE = 1).
The analog output (VOUT) is disabled and biased at VREF.
The channel status (CSTAT) bit in the SLIC device I/O Direction and Channel Status Register is set to 0.
D
D
D
D
D
0
0
0
0
0
7
7
7
7
7
Zarlink Semiconductor Inc.
D
D
D
D
D
page 36
0
0
0
0
0
6
6
6
6
6
45
of the section Operating the QLSLAC Device.
D
D
D
D
D
0
0
0
0
0
5
5
5
5
5
D
D
D
D
D
0
0
0
0
0
4
4
4
4
4
D
D
D
D
D
0
0
0
0
1
3
3
3
3
3
D
D
D
D
D
0
0
1
1
1
2
2
2
2
2
D
D
D
D
D
0
1
0
1
1
1
1
1
1
1
D
D
D
D
D
0
0
0
0
0
0
0
0
0
0
page
82.