LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 48

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

These commands do not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 9Ah.
4A/4Bh Write/Read Channel Enable and Operating Mode Register
RSVD
Robbed-bit Mode (Global parameter)
VOUT Mode (Global parameter)
Low Power Mode (Global parameter)
Channel Enable 4
Channel Enable 3
Channel Enable 2
Channel Enable 1
* Power Up and Hardware Reset (RST) Value = 0Fh.
4D/4Fh Read Real-Time Data Register
Real Time Data
Command
I/O Data
Command
Output Data
MPI Command
R/W = 0: Write
R/W = 1: Read
MPI Command
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without clearing the interrupt.
CSEL = 11xx
CSEL = 1010*
Reserved for future use. Always write as 0, but 0 is not guaranteed when read
RBE = 0*
RBE = 1
VMODE = 0*
VMODE = 1
LPM
EC4 = 0
EC4 = 1*
EC3 = 0
EC3 = 1*
EC2 = 0
EC2 = 1*
EC1 = 0
EC1 = 1*
CDA
CDB
CDA
CDB
1
1
2
2
Reserved
8.192 MHz is the default
Robbed-bit Signaling mode is disabled
Robbed-bit Signaling mode is enabled on PCM receiver if
VOUT = VREF through a resistor when channel is deactivated
VOUT high impedance when channel is deactivated
LPM reduced the power in the QSLAC device, but it is not needed and not used in the
QLSLAC device
Disabled, channel 4 cannot receive commands
Enabled, channel 4 can receive commands
Disabled, channel 3 cannot receive commands
Enabled, channel 3 can receive commands
Disabled, channel 2 cannot receive commands
Enabled, channel 2 can receive commands
Disabled, channel 1 cannot receive commands
Enabled, channel 1 can receive commands
Debounced data bit 1 on channel 1
Data bit 2 or multiplexed data bit 1 on channel 1
Debounced data bit 1 on channel 2
Data bit 2 or multiplexed data bit 1 on channel 2
RSVD
CDB
D
D
0
0
7
7
4
Zarlink Semiconductor Inc.
RBE
D
CDA
1
D
6
1
6
4
VMODE
48
CDB
D
D
0
0
5
5
3
CDA
LPM
D
D
0
0
4
4
3
CDB
EC4
D
D
1
1
3
3
2
CDA
EC3
D
D
1
0
2
2
2
µ
-law is selected
CDB
EC2
D
D
C
1
1
1
1
CDA
R/W
EC1
D
D
1
0
0
1