LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 37

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

14. The supervision debounce time is set to 8 ms.
15. The chopper clock frequency is set to 256 kHz, but the chopper clock is turned off.
16. The E1 Multiplex state is turned off (E1 is Hi-Z) and the polarity is set for high going pulses.
17. No signaling on the PCM highway (PCM/MPI mode).
SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the performance
of the QLSLAC device for the system. Figure 23 shows the QLSLAC device signal processing and indicates the programmable
blocks.
The advantages of digital filters are:
n
Two-Wire Impedance Matching
Two feedback paths on the QLSLAC device synthesize the two-wire input impedance of the SLIC device by providing a
programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog gain
of −0.9375 • GIN to +0.9375 • GIN from VIN to VOUT. (See GIN in
programmable digital filter providing an additional path and programming flexibility over the AISN in modifying the transfer
function from V
input impedances.
Frequency Response Correction and Equalization
The QLSLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be programmed for
line equalization and to correct any attenuation distortion caused by the Z filter.
Transhybrid Balancing
The QLSLAC device’s programmable B filter is used to adjust transhybrid balance (MPI Commands 86/87h and 96/97h, GCI
Commands COP 5 and COP 8). The filter has a single pole IIR section (BIIR) and an eight-tap FIR section (BFIR), both operating
at 16 kHz.
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.90 modems
V
IN
GIN
V
Full
Digital
Loopback
(FDL)
OUT
IN
to V
OUT
. Together, the AISN and the Z-Filter enable the user to synthesize virtually all required SLIC device
AISN
+
VREF
*
AX
*
Figure 23. QLSLAC Device Transmission Block Diagram
AR
*
ADC
DAC
* programmable blocks
polator
mator
Deci-
Inter-
+
Zarlink Semiconductor Inc.
Z
*
polator
High Pass Filter (HPF)
mator
Deci-
Inter-
37
+
B
*
Electrical Characteristics, on page
GR
GX
*
*
Lower Receive
Gain (LRG)
X
R
*
*
LPF &
HPF
LPF
Cutoff Receive
TSA Loopback
0
Path (CRP)
pressor
pander
(TLB)
Com-
Ex-
1 kHz Tone
(TON)
13.) The Z filter is a
TSA
TSA
Cutoff
Transmit
Path
(CTP)
Digital
RX
Digital
TX