LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 41

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

receive (digital-to-analog) path is involved. There is no change of operation to the transmit path and PCM data coming out of the
QLSLAC device will always contain complete PCM byte data for each time slot, regardless of robbed-bit signaling selection.
In the absence of actual PCM data for the affected time slots, there is an uncertainty of the legitimate value of this bit to accurately
reconstruct the analog signal. This bit can always be assumed to be a 1 or 0; hence, the reconstructed signal is correct half the
time. However, the other half of the time, there is an unacceptable reconstruction error of a significance equal to the value
weighting of the LSB. To reduce this error and provide compatibility with the robbed bit signaling scheme, when in the robbed-bit
signaling mode, the QLSLAC device ignores the LSB of each received PCM byte and replaces its value in the expander with a
value of half the LSB’s weight. This then guarantees the reconstruction is in error by only half this LSB weight. In the expander,
the eight bits of the companded PCM byte are expanded into linear PCM data of several more bits within the internal signal
processing path of the device. Therefore, accuracy is not limited to the weight of the LSB, and a weight of half this value is
realizable.
When this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte requires its LSB
substituted with the half-LSB weight. This substitution only occurs for valid PCM time slots within frames for which this robbed bit
has been designated. To determine which time slots are affected, the device monitors the frame sync (FS) pulse. The current
frame is a robbed-bit frame and this half-LSB value is used only when this criteria is met:
n
The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 24, if the above criteria is met, and if FS is
high for two consecutive falling edges of PCLK then low for the third falling edge, it is considered a robbed-bit frame. Otherwise,
it is a normal frame.
Default Filter Coefficients
The QLSLAC device contains an internal set of default coefficients for the programmable filters. The default filter gains are
calculated calculated based on the application circuit shown on
a current gain of 500 (K1). The transmit relative level is set to +0.28 dBr, and the receive relative level is set to –4.39 dBr. The
equalization filters (X and R) are not optimized and the Z and B filters are set to zero. The nominal input impedance was set to
812 Ω. If the SLIC device circuit differs significantly from this design, the default gains cannot be used and must be replaced by
programmed coefficients. The balance filter (B) must always be programmed to an appropriate value.
To obtain this above-system response, the default filter coefficients are set to produce these values:
GX gain = +6 dB, GR gain = –8.984 dB
AX gain = 0 dB, AR gain = 0 dB, input attenuator on (DGIN = 0)
R filter: H(z) = 1, X filter: H(z) = 1
Z filter: H(z) = 0
B filter: H(z) = 0
AISN = cutoff
The RBE bit is set, and
The device is in the µ-law companding mode, and
The current frame sync pulse (FS) is two PCLK cycles long, and
The previous frame sync pulse (FS) was not two PCLK cycles long.
PCLK
PCLK
FS
FS
Figure 24. Robbed-Bit Frame
Normal Frame (Not Robbed-Bit)
Zarlink Semiconductor Inc.
Robbed-Bit Frame
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87. This SLIC device has a transmit gain of 0.5 (GTX) and