TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 102

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
10.6 LINE INTERFACE
10.7 APS INTERFACE
Four serial line interfaces with differential input/output and integrated clock recovery and
synthesis are provided.
The device supports two modes: either a single STM-4/OC-12 signal, or four STM-1/OC-3
signals.
The device’s system clock is the time base for the transmit SDH/SONET line output(s).
Each individual line interface can be powered down via a memory mapped register.
Frame alignment is recovered from the A1-A2 bytes of the received signals.
The OOF anomaly and the dLOF defect will be detected according to the latest ITU/ETSI/
ANSI standards.
The following additional functions are provided:
AIS will be inserted per line on detection of dLOF, on detection of dLOS, optionally on the
externally detected Signal Detect or under software control.
The APS Port transports the payload and APS signaling between two mate devices. The APS
finite state machine itself needs to be implemented by the external host software. The
resulting bridge and switch requests are performed by configuring the cross connect.
A single 622.08 Mbit/s LVDS serial APS interface with differential input/output is provided.
Clock recovery and synthesis are integrated.
The device’s system clock is the time base for the transmit APS interface output.
The APS port interface can be powered down via a memory mapped register.
The APS Interface characteristic information consists of:
• Line Interface #1 can handle 622.08 Mbit/s or 155.52 Mbit/s data rate for STM-4/OC-12,
• Line Interfaces #2 - #4 can handle 155.520 Mbit/s data rate for STM-1/OC-3 applications.
• Four (one for each line interface) active high status inputs to monitor the external optical
• Four (one for each line interface) output control signals under microprocessor command
• Four (one for each line interface) reference clocks derived from the received signal. The
STM-1/OC-3 applications respectively.
transceivers for low power status.
to control each individual external optical transceiver.
rate of these reference clocks will be selectable per line.
aAIS
=
+
+
+
not SignalDetect
dLOS
dLOF
Framer AIS Force
[line]
[line]
-
Operation
* not LOS_AIS_Insert_Disable
* not LOF_AIS_Insert_Disable
[line]
[line]
-
* not SignalDetect_AIS_Insert_Disable
[line]
[line]
1 0 2 o f 2 26
[line]