TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 154

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
The behavior of the ATM/PPP related counters depends on wether or not the one second
mechanism is enabled.
When the one second mechanism is enabled the counters behave in the same manner as the
SDH/SONET counters. This means that at the one second boundary, the contents of each
counter is latched into its one second shadow register and the counter is cleared. The one
second shadow registers will hold their value during the entire period between two
subsequent one second boundaries.
When the one second mechanism is disabled, the software has full control over the moment a
counter is copied to its shadow register. If the software does a read access to a shadow
register, the content of the related counter is copied to this shadow register and the counter is
cleared. The shadow register will hold its value until the software again does a read access to
it. Note that only the counter related to the accessed shadow register will be copied and
cleared, all other counters are left untouched. Note also that in case of a 24-bit counter, the
software first has to read the 2 least significant bytes. At this moment the counter is copied into
its shadow registers and cleared. Reading the most significant byte will not clear the counter.
The latching mechanism can be configured for the ATM/PPP Mapper and the ATM/PPP
Demapper separately.
All these counters are saturating: counting will stop when the maximum count value is
reached.
The one second boundary is generated by the internal one second clock which is either
derived from the PHAST-12P system clock or from the external REFONESECCLK input lead.
The performance counters can be reset by writing 0x91 into the ResetCounters register.
OneSecondPM_Enable
• PPP demapping:
• PPP mapping
• Number of idle/unassigned cells inserted
• Number of corrupted cells received from the FIFO
• Number of packets forwarded to the FIFO
• Number of frames affected by a FIFO overflow,
• Number of frames with an FCS error, abort sequence or mismatched Address/Control
• Number of frames longer than the maximum frame length
• Number of frames shorter than the minimum frame length
• Number of good packets received from the FIFO
• Number of frames for which a FIFO underflow occurs while the frame is being
• Number of packets for which the error signal on the POS-PHY Level 2 interface was
-
High Order Pointer Tracking, Retiming and Pointer Generation
fields
transmitted
asserted during the last word transfer of that packet
0 (Default)
1
Clear-on-read mechanism: the counters are copied to the
shadow registers and cleared upon a read access.
One second mechanism: the counters are copied to the shadow
registers and cleared every second.
Description
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