TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 196

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
Offset
Offset
0x02A0
0x0014 PPP
0x0000
0x0200 11 - 0
0x0240
0x0280 7 - 0
12.14 POS/ATM MAPPER
0
1
2
3
4
5
Bits
Bits
TransparentMode
CheckHeader_Enable
StripHeader_Enable
CheckFCS_Enable
StripFCS_Enable
FCS32_Enable
PerfCounters_Shadow
CorrDefects_Mask
Common_Config
IngressFIFO_Reset
AUG1_Mode_Config
Table 53: POS/ATM Demapper PHY Configuration
Name
Name
Table 54: POS/ATM Mapper
-
Memory Maps and Bit Descriptions
Init
Init
0xFFF rw
0x0 Enables transparent mode when 0x1. In transparent mode the HDLC
0x1 Enables Address and Control fields check when 0x1. When enabled,
0x1 Enables Address and Control fields stripping when 0x1.
0x1 Enables FCS check when 0x1. When disabled, all consequent
0x1 Enables FCS stripping when 0x1.
0x1 32 bit FCS size when 0x1, 16 bit FCS size otherwise.
0x0 rw
functionality is bypassed, i.e., all bytes are passed through
transparently (no framing, no byte destuffing, no abort detection, no
FCS processing).
Applies to PPP mode only.
packets of which the address field is not equal to 0xFF and/or the
Control field is not equal to 0x03 are filtered (discarded).
Applies to PPP (no transparent) mode only.
Applies to PPP (no transparent) mode only.
actions (status, counters, interrupt generation and signaling on POS-
PHY interface) are also disabled.
Applies to PPP (no transparent) mode only.
Applies to PPP (no transparent) mode only.
Applies to PPP (no transparent) mode only.
ro/cor
rw
rw
Access
(T_POS_ATM_MAPPER)
Array (12) of T_MAP_PerfCounters
Offset between two elements = 0x10.
Array index indicates the PHY.
Performance counters.
Note: In case the one second performance monitoring
mechanism is enabled, the access type is read-only,
otherwise it is clear-on-read.
Defects mask. See CorrDefects_Unlatched.
Applies to PPP mode only.
T_MAP_Common_Config
General configuration.
Microprocessor Controlled Reset for the Ingress FIFO.
Writing the value 0x91 to this register generates a Soft
Reset for the Ingress FIFO. Reset is active as long as this
register contains the value 0x91.
T_AUG1_Mode_Config
AUG-1 mode configuration.
-
(T_DMP_Phy_Config)
Description
Description
(See page
(See page
177.)
(See page
198.)
1 9 6 o f 2 26
197.)