TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 144

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.14 UTOPIA INTERFACE
11.14.1 Transmit Interface
11.13.2.4 Per PPP Stream Counters
The sum of the number of packets received from Tx FIFO, the number of frames for which a
Tx FIFO underflow occurred and the number of packets for which the error indication was
asserted is equal to the total number of packets forwarded.
All PPP packets must have a minimum length of 10 bytes.
Translation of the 12 configurable 5-bit POS-PHY addresses into PPP packet stream
addresses (0, 1, . . , 11) is done in the POS-PHY interface block.
When mapping into a certain SDH/SONET stream is disabled, software has to configure the
POH Generator to insert the UNEQUIPPED activation pattern in the corresponding path.
This is an UTOPIA Level 2 interface with cell level handshaking for up to twelve VC-3/STS-1
SPE cell streams, four VC-4/STS-3c SPE cell streams, or a single VC-4-4c/STS-12c SPE cell
stream.
Each stream corresponds to a PHY port, to which a unique 5-bit address between 0x00 and
0x1E can be assigned. 0x1F is the null-PHY address.
Note: the UTOPIA Level 1 (single PHY) standard specifies both cell-level and octet-level
handshaking. In single PHY mode, the PHAST-12P can be connected to and ATM layer
device that is Level 1 compliant which does either cell-level or octet-level handshaking.
The transmit interface consists of the following leads:
The maximum clock frequency is 50 MHz and the data and control signals are transferred on
the rising edge of this clock.
• Number of packets (0 . . . 2
• Number of frames (0 . . . 255) for which a Tx FIFO underflow occurred while the frame
• Number of packets (0 . . . 255) for which the error signal on the POS-PHY interface
• Input clock PPUTTXCLK
• Input address PPUTTXADDR(4-0)
• Input data PPUTTXDATA(15-0)
• Input parity PPUTTXPRTY
• Input start of cell PPUTTXSOPC
• Input write enable PPUTTXENB
• Output cell available PPUTPTPACLAV(3-0)
-
High Order Pointer Tracking, Retiming and Pointer Generation
is being transmitted
was asserted during the last word transfer of that frame
24
-1) received from Tx FIFO (shared with ingress ATM)
-
1 4 4 o f 2 26