TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 206

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
0x000C
0x000A
0x000E
0x001E
0x0006
0x0008
0x0010
0x0012
0x0014
0x0000
Offset
Offset
0
0
0
1 - 0
1 - 0
4-0
4-0
2 - 0
12 - 3
Bits
Bits
RxRefSelect
TxPLL_Cap_Enable
RxPLL_Cap_Enable
TxRefFreq
RxRefFreq
TxPLL_PowerDown
RxPLL_PowerDown
CDRTune
PLLTune
PhaseInterpolator
DigitalLoopFilter
Name
Name
Table 70: CDR Tuning Configuration
-
Memory Maps and Bit Descriptions
Table 69: PLL Control
Init
0x1F
0x1F
Init
0x4A
0x0
0x0
0x0
0x0
0x0
0x4
Receive reference clock external source selection for the PLL in the receive
section.
•
•
Enables the external capacitor in the Transmit PLL when 0x1.
Reserved. Must be set to 0.
Transmit PLL reference clock frequency.
Indicates the frequency of the reference clock for the PLL.
•
•
•
•
Receive PLL reference clock frequency.
Indicates the frequency of the reference clock for the PLL.
•
•
•
•
Power Down for the Transmit PLL modules.
Must be set to 0x0 at power-up.
Power Down for the RxPLL modules.
Must be set to 0x0 at power-up.
Array (5) of T_CDRTune
Offset between two elements = 0x2.
Array index indicates the interface.
•
•
•
•
•
T_PLLTune
Reserved.
Set to 0x4 for STM-4/OC-12 application
Set to 0x1 for STM-1/OC-3 application
Reserved.
Set to 0x4a for STM-4/OC-12 application
Set to 0x5c for STM-1/OC-3 application
0x0: REFRXCLK is used as reference clock
0x1: REFTXCLK1/REFTXCLK2 is used as reference clock, the selec-
tion between the transmit reference clocks is made using the TxRef-
Select field
0x0: 19.44 MHz, REFTXCLK1 or REFTXCLK2
0x1: 77.76 MHz, REFTXCLK1 or REFTXCLK2
0x2: 155.52 MHz, REFTXCLK2
0x3: 622.04 MHz, REFTXCLK2. In this mode the Transmit PLL must
be bypassed. Mind the Transmit PLL is actually still working then,
although it’s output is never used.
0x0: 19.44 MHz, REFRXCLK or REFTXCLK1 or REFTXCLK2
0x1: 77.76 MHz, REFRXCLK or REFTXCLK1 or REFTXCLK2
0x2: 155.52 MHz, REFTXCLK2
0x3: Reserved
Array index 0: Line 1
Array index 1: Line 2
Array index 2: Line 3
Array index 3: Line 4
Array index 4: APS
(See page
(T_PLL_Control)
207.)
(See page
(T_CDRTune)
-
Description
Description
206.)
2 0 6 o f 2 26