TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 129

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 2 9 o f 2 26
A9
cE-RDI(-S)(-C)(-P)
11.7 TOH PORT INTERFACE
11.7.1 Transmit TOH Port Interface
(Range 0 to 8)
Row number
A8
a-1
The transmit TOH port interface allows insertion of the RSOH and MSOH bytes into the TOH.
All received TOH bytes are output on the receive TOH port interface.
Each interface consists of clock, data, data enable, address and address enable lines.
The address is a 10-bit word according to the (a, b, c) format specified by ITU-T G.707/Y.1322
clause 9.2.1 and Figure 9-1:
This port interface allows insertion of the RSOH and MSOH bytes into the TOH. The TOH
port interface is used to request any of the TOH bytes for either one STM-4 or four STM-1
frames from the outside world. Note the BIP bytes (B1, B2) have a special meaning, these
can be used as an error mask on the calculated BIP.
The Transmit TOH Port consists of following leads:
• Optionally bypass the POH monitor: the entire high order path is passed through without
• Output Transmit TOH Port Clock TOHTXCLK
• Output Transmit TOH Port Address Latch Enable TOHTXALE
• Output Transmit TOH Port Address TOHTXADDR
• Output Transmit TOH Port Data Latch Enable TOHTXDLE
• Input Transmit TOH Port Data TOHTXDATA
processing.
Note: The High order POH Monitor should be bypassed for unused high-order paths.
A7
- High Order Pointer Tracking, Retiming and Pointer Generation -
[path]
A6
=
*
*
*
A5
dE-RDI(-S)(-C)(-P)
(not dSSF
(not dUNEQ
+ not dTTIZERO
+ UNEQ_RDI_Inhibit_Disable * TTIZERO_RDI_Inhibit_Disable)
(not dTIM
(Multi-)Column number
A4
(Range 0 to 8)
[path]
[path]
b-1
[path]
A3
+ TIM_RDI_Inhibit_Disable)
+ SSF_RDI_Inhibit_Disable
[path]
* not UNEQ_RDI_Inhibit_Disable
[path]
A2
* not TTIZERO_RDI_Inhibit_Disable
STM-1/OC-3 Line
Interleave Depth
(Range 0 to 3)
(Range 0 to 3)
Multi-Column
A1
c-1
PRELIMINARY TXC-06412B-MB, Ed. 2
A0
PHAST-12P Device
Line Interface Mode
STM-4/OC-12 Mode
STM-1/OC-3 Mode
DATA SHEET
TXC-06412B
June 2005