TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 165

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 6 5 o f 2 26
11.23 BOUNDARY SCAN
11.23.1 Introduction
11.23.2 Boundary Scan Operation
The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that con-
forms to the IEEE 1149.1 standard. This standard provides external boundary scan functions
to read and write the external Input/Output leads from the TAP for board and component test.
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has
been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized
scan architecture that provides observability and controllability for the interface leads of the
device. As shown in
or output lead to be observed or tested (bidirectional leads may have two cells). The bound-
ary scan capability is based on a Test Access Port (TAP) controller, instruction and bypass
registers, and a boundary scan register bordering the input and output leads. The boundary
scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select
(TMS), Test Data Input (TDI) and Test Reset (TRS) and a Test Data Output (TDO) output sig-
nal. Boundary scan signal timing is shown in
The TAP controller receives external control information via a Test Clock (TCK) signal and a
Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. Detailed
information on the operation of this state machine can be found in the IEEE 1149.1 standard.
The serial scan path architecture consists of an instruction register, a boundary scan register
and a bypass register. These three serial registers are connected in parallel between the Test
Data Input (TDI) and Test Data Output (TDO) signals, as shown in
The boundary scan function can be reset and disabled by holding lead TRS low. When
boundary scan testing is not being performed the boundary scan register is transparent,
allowing the input and output signals to pass to and from the PHAST-12P device’s internal
logic. During boundary scan testing, the boundary scan register may disable the normal flow
of input and output signals to allow the device to be controlled and observed via scan opera-
tions.
The maximum frequency the PHAST-12P device will support for boundary scan is 10 MHz.
The timing diagrams for the boundary scan interface leads are shown in
The instruction register contains three bits. The PHAST-12P device performs the following
three boundary scan test instructions:
- High Order Pointer Tracking, Retiming and Pointer Generation -
The EXTEST test instruction (000) provides the ability to test the connectivity
of the PHAST-12P device to external circuitry.
The SAMPLE test instruction (010) provides the ability to examine the bound-
ary scan register contents without interfering with device operation.
The BYPASS test instruction (111) provides the ability to bypass the PHAST-
12P boundary scan and instruction registers.
Figure
50, one cell of a boundary scan register is assigned to each input
Figure
22.
PRELIMINARY TXC-06412B-MB, Ed. 2
Figure
PHAST-12P Device
Figure
50.
DATA SHEET
50.
TXC-06412B
June 2005