TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 16

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
1.3 APS PORT INTERFACE
1.4 RS/SECTION LAYER PROCESSING
1.5 MS/LINE LAYER PROCESSING
• Transmit clock synthesis
• Per Line Interface:
• Single 622.08 Mbit/s LVDS serial interface:
• The APS port transports the payload and APS signaling between two mate devices. The
• A1/A2 frame alignment
• J0 Trail Trace Identifier:
• Scrambling and descrambling
• B1 BIP-8 insertion and monitoring
• D1-D3 DCC accessible via the DCC port
• All received RSOH bytes are stored in on-chip memory and transmitted on the TOH port
• All RSOH bytes can be inserted from on-chip memory or from the TOH port
• B2 BIP-24/96 insertion and monitoring
• D4-D12 DCC can be accessible via the DCC port
• Insertion and monitoring of remote information (RDI, REI)
• Line Interfaces #2 to #4 handle 155.52 Mbit/s signals and are only used in STM-1/
• Receive clock recovery
• Loss of Signal detection
• Receive 19.44 MHz (STM-1/OC-3 mode) or 77.76 MHz (STM-4/OC-12 mode) clock
• General purpose input/output pins
• Receive clock recovery
• Transmit clock synthesis
• Receive 77.76 MHz clock output reference
• Transport of high order path data for four STM-1/OC-3 signals or one STM-4/OC-12
• Transport of K1/K2 APS signal, signal fail and signal degrade indications for up to four
APS finite state machine itself needs to be implemented by the external host software.
The resulting bridge and switch requests are performed by configuring the cross-connect.
• Out of frame and loss of frame detection
• Insertion and monitoring of single repeating byte and 16-byte trace messages
• Trace identifier mismatch detection
• Degraded signal and excessive bit error detection
• Block and bit error performance monitoring counters
OC-3 mode
output reference
signal between two PHAST-12P devices
lines between two PHAST-12P devices
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Features
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