TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 148

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.15.2 Receive Interface
11.15.2.1 Shared Settings for all POS-PHY Ports
The receive interface consists of the following leads:
The maximum clock frequency is 50 MHz and the data and control signals are transferred on
the rising edge of this clock.
• Input clock PPUTRXCLK
• Input address PPUTRXADDR(4-0)
• Output data PPUTRXDATA(15-0)
• Output parity PPUTRXPRTY
• Output start of packet PPUTRXSOPC
• Output end of packet PPRXEOP
• Output word modulo PPRXMOP
• Output error PPRXERR
• Input read enable PPUTRXENB
• Output data valid PPRXVAL
• Output polled PHY packet available PPUTPRPACLAV(3-0)
• Enable/disable entire interface (shared with Rx UTOPIA)
• PHY Mode: single-PHY or multi-PHY (shared with Rx UTOPIA)
• Following two Status indication Modes are possible (mix is not supported - shared with Tx
• Odd or even parity (shared with Rx UTOPIA)
• Parity over data or data and control signals (shared with Rx UTOPIA)
• FIFO threshold: the number of words which has to be available in the Rx FIFO to trigger
UTOPIA):
• Direct status: at most 4 DRPA’s are used, at most 4 PHY’s are possible
• Multiplexed status with full addressing: 1 PRPA (PRPA0) signal is used, at most 31
the high assertion of the related CLAV signal. This value must always be larger than 0.
Not that setting this value to X means that once the reading of a packet from the FIFO is
started, at least X number of words can be read (shared with Rx UTOPIA)
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High Order Pointer Tracking, Retiming and Pointer Generation
PHY’s are possible
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