TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 97

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

9 7 o f 2 2 6
MPCLK
System Clock (= LINETXCLK)
APSRXCLK
MPCLK
System Clock (= LINETXCLK)
PPUTTXCLK
MPCLK
System Clock (= LINETXCLK)
PPUTRXCLK
10.3 RESET
10.2.2 Loss of Clock Detection
10.3.1 External Lead Controlled Hardware Reset
10.3.2 Microprocessor Controlled Hardware Reset (RESETH)
Clock Domain
All clocks, except the microprocessor clock, are monitored for Loss of Clock. The clock to be
monitored is divided by LocDivider + 1.
Loss of Clock is detected as follows:
Note: The Loss of Clock detector can only operate correctly if the optical transceiver
generates a constant output (no transitions) on the receive side when there is no valid
incoming optical signal.
Hardware Reset (Active Low): The use of this lead at power-up is mandatory. Holding this
lead low for at least 50ns causes all the registers in the device to be reset.
When written with the value 0x91H all registers in the device will be reset but with a few
exceptions.
The registers in the following blocks will not be reset:
These are the registers that operate in the microprocessor clock domain.
• Entry: when LOC_EntryThreshold microprocessor clock cycles have passed without
• Exit: when LOC_ExitThreshold transitions are detected the divided clock
transitions on the divided clock to be monitored
• Microprocessor interface
• Global control
• Reset generator
• Interrupt
• Clock recovery / clock synthesis / SerDes
• JTAG Master
Receive APS Port
Ingress UTOPIA/POS-PHY Level 2 Interface
Egress UTOPIA/POS-PHY Level 2 Interface
- Operation -
Blocks
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005