TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 48

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
MPINTR
Symbol
MPACK
Symbol
MPCLK
MPWR
MPA13
MPA12
MPA10
MPA09
MPA08
MPA07
MPA06
MPA05
MPA04
MPA03
MPA02
MPA01
MPA00
MPA11
GENERIC MOTOROLA - HOST PROCESSOR INTERFACE
Lead No.
Lead No.
M1
C2
D2
C1
G4
D1
B3
B1
E4
E3
F4
B2
E2
F3
E1
F2
L2
L1
I/O/P
I/O/P
O(T) LVCMOS
O
I
I
I
LVCMOS
LVTTL Write Strobe (Active Low): This active low lead initiates
LVTTL Microprocessor Clock: This lead is the clock sourced by
LVTTL Address Bus: These leads are the address bus used by
-
24mA
Type
Type
8mA
Lead Descriptions
a write transfer between the host processor and the
PHAST-12P.
Intel notation: WR
Ready: For a write access, an active edge on this lead indi-
cates that data is written to the addressed memory loca-
tion. For a read access, an active edge on this lead
indicates that the data to be read from the addressed mem-
ory location is available on the data bus.
Active level depends on MPACKLEVEL.
Intel notation: RDY
Interrupt: This lead signals an interrupt request to the host
processor.
Active level depends on MPINTLEVEL.
the microprocessor being interfaced to this device.
Its max. frequency is 50 MHz.
Motorola notation: CLK
the host processor for accessing the PHAST-12P for a
read or write cycle.
MPA13 is the most significant bit in the location’s
address.
Motorola notation: A[ ]
-
Name/Function
Name/Function
4 8 o f 2 26