TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 155

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 5 5 o f 2 26
1.
11.21 DEFECTS AND INTERRUPTS
( x ) is used to indicate a logical ‘
11.21.1 Unlatched Defects (Correlated)
11.21.2 Latched Defects
11.21.3 Defects Mask
11.21.4 Interrupts
Defects representing the current status of the device are correlated to fault causes (correlated
defects). This inhibition process avoids the unnecessary generation of interrupts, when a
defect that is at an high hierarchy leads to the generation of multiple lower order defects.
Unlatched defects are read-only.
Changes in the state of defects are latched by the PHAST-12P. The edge on which latching
occurs is configurable through the LatchForIntCtrl control register:
Latched defects are cleared by a clear-on-write-1 mechanism (COW-1). This way software/
firmware can clear a defect when it will be handled. Software must never write a ‘1’ to a
latched defect that was previously read to be ‘0’, because between the read and the write the
defect may become active and will be cleared without software knowing it was active.
Each latched defect can optionally contribute to the device hardware interrupt. The
contribution of each individual latched defect can be enabled/disabled by clearing/setting the
corresponding mask
The contribution of groups of latches can in turn be combined into a summary latch with
associated mask, forming an interrupt tree
At the device top level, the general interrupt summary latches and the APS interrupt summary
latches contribute to the interrupt:
The hardware interrupt capability is enabled by setting the HINTEN control bit. While
disabled, the hardware interrupt indication INT/IRQ output lead is inactive. When enabled, the
device top level hardware interrupt is
Summary
device interrupt
HINT
INT/IRQ output lead
• Both rising and falling edges are latched (default)
• Only rising edges are latched, or
• Only falling edges are latched
- High Order Pointer Tracking, Retiming and Pointer Generation -
General_Interrupt
APS_Interrupt
( Defect_Latch
1
OR
:
’ of a number of logical expressions ( x ).
( Summary
( HINT
k AND
i AND
AND
OR
i AND
i AND
not APS_Mask
HINTEN )
not General_Mask
not Defect_Mask
not Summary_Mask
k
)
i
i
)
)
PRELIMINARY TXC-06412B-MB, Ed. 2
i
)
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005