TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 130

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.8 DCC PORT INTERFACE
11.7.2 Receive TOH Port Interface
11.8.1 Transmit DCC Port Interface
The transmit TOH Port protocol is as follows (see
Note: Configuration of the Transmit TOH Port interface is done in the memory map of the
TOH Generator (see
the TOH bytes internal memory by setting the most significant bit of the corresponding
memory entry to ‘1’.
All received RSOH and MSOH bytes are sent over a serial Receive TOH Port interface. The
values sent out on this interface are the raw, unprocessed values, except for B1 and B2,
where an error mask is calculated (ones indicate the errored bits).
The Receive TOH Port consists of following leads:
The Receive TOH Port protocol is as follows (see
Note: Configuration of the Receive TOH Port interface is done in the memory map of the
TOH and DCC Port (see
TOH_Port_Enable setting. No bytes will be sent out when this port is disabled.
The Transmit and the Receive DCC Port interfaces provide an interface to the RS or MS DCC
bytes. The interface is a constant bit-rate serial interface, each consisting of a clock and a
data line.
The Transmit DCC ports are constant bit-rate ports that provide a possible source for either
the RS or the MS DCC bytes in the outgoing STM-4 or the four STM-1 frames. In STM-4
mode, only the first DCC Port is active.
• Output Receive TOH Port Clock TOHRXCLK
• Output Receive TOH Port Address Latch Enable TOHRXALE
• Output Receive TOH Port Address TOHRXADDR
• Output Receive TOH Port Data Latch Enable TOHRXDLE
• Output Receive TOH Port Data TOHRXDATA
1. The 10-bit address for the requested byte is output on TOHTXADDR, most significant
2. A one cycle gap is left open.
3. The Data Latch Enable TOHTXDLE is asserted and the 8-bit data word is sampled
1. The 10-bit address for the transmitted byte is output on TOHRXADDR, most signifi-
2. A one cycle gap is left open.
3. The 8-bit data of the transmitted TOH byte is output on TOHRXDATA. During this
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High Order Pointer Tracking, Retiming and Pointer Generation
bit first. During this time the Address Latch Enable TOHTXALE is asserted.
on the input TOHTXDATA, most significant bit first.
cant bit first. During this time the Address Latch Enable TOHRXALE is asserted.
time the Data Latch Enable TOHRXDLE is asserted.
Table
Table
34). Selection of the TOH Port as source for a TOH byte is done in
37). The Receive TOH Port interface has to be enabled by the
Figure
Figure
6):
5):
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1 3 0 o f 2 26