TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 98

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
10.4 POWERUP, INITIALIZATION AND STARTUP
10.3.3 Microprocessor Controlled Reset Per Clockdomain
There are 6 major interfaces. For each of these there is a separate microprocess controlled
reset available. Reset is activated by writing the value 0x91 H to the corresponding register.
These software resets may only be asserted when RESETH is equal to 0x91. They may be
deasserted at anytime.
After powerup and external reset of the device, no internal clocks are active. This section
describes the way the necessary clocks need to be brought up and the initialization of the
device.
The first clock present in the device is the external microprocessor clock. The registers which
are needed to bring up the internal clocks are located in the clock domain from this external
microprocessor clock.
The clock domains which must be brought up next are:
The Ingress and Egress UTOPIA/POS-PHY interfaces use external clocks. These clocks
must be running in order to access the register in these domains.
At this stage of the process, the hardware interrupt can be enabled through the HINTEN field
(see
properly disabled here.
It is advised to unmask the Global Control Interrupt now. In the Global Control block, the Loss
of System Clock and Loss of Clock for the active lines must be unmasked to enable the
hardware interrupt for events on the Loss of Clock detection.
After this, the Clock Recovery/Clock Synthesis block must be configured and powered up
(see section
It is recommended to leave RESETH (see
deasserted, the device will start a reset sequence for all of its internal RAMs. The
RamResetDone record in the Global Control block (see
domains have finished resetting their RAMs.
Once all the necessary clock domains are powered up, and the corresponding RAMs are
reset, the device will not yet be operational. Operation is halted so the device can be
configured in a clean way. Once the configuration is done, DeviceInitialized field in Global
Control can be set to 1 and the device will start its normal operation.
• System Clock
• Rx Line 1 Clock
• Rx Line 2 Clock
• Rx Line 3 Clock
• Rx Line 4 Clock
• Rx APS Clock
• RxLine1_Reset ... RxLine4_Reset: Reset in the RxLine 1 ... 4 clock domain
Table 7
Powerup of the
of
Memory Maps and Bit Descriptions
CDR/CS).
-
Operation
-
Table
6) asserted until this point. Once RESETH is
section). The interrupt masks must be
Table
2) indicates which clock
9 8 o f 2 26