TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 146

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.15 POS-PHY INTERFACE
11.15.1 Transmit Interface
11.14.2.1 Shared Settings for all UTOPIA PHY Ports
11.14.2.2 Per UTOPIA PHY Port Settings
11.14.2.3 Per CLAV Setting
This is a POS-PHY Level 2 interface with packet level handshaking for up to twelve VC-3/
STS-1 SPE cell streams, four VC-4/STS-3c SPE cell streams, or a single VC-4-4c/STS-12c
SPE cell stream.
Each stream corresponds to a PHY port, to which a unique 5-bit address between 0x00 and
0x1E can be assigned. 0x1F is the null-PHY address.
The transmit interface consists of the following leads:
• Enable/disable entire interface (shared with Rx POS-PHY)
• PHY Mode: single-PHY or multi-PHY (shared with Rx POS-PHY)
• Status Indication Mode: (shared with Rx POS-PHY)
• Odd or even parity (shared with Rx POS-PHY)
• Parity over data or data and control signals (shared with Rx POS-PHY)
• 16-bit databus width
• FIFO threshold: the number of words which has to be available in the Rx FIFO to trigger
• Direct status: at most 4 CLAV’s are used, at most 4 PHY’s are possible
• Multiplexed status with full addressing: 1 CLAV (CLAV0) signal is used, at most 31
• Multiplexed status with group addressing: 4 CLAV’s are used, at most 31 PHY’s are
the high assertion of the related CLAV signal (shared with Rx POS-PHY). For UTOPIA it
is mandatory to set this value to 27
• Enable/disable PHY port (shared with Rx POS-PHY)
• PHY Port address (shared with Rx POS-PHY)
• Timeslot for direct status (shared with Rx POS-PHY)
• Input clock PPUTTXCLK
• Input address PPUTTXADDR(4-0)
• Input data PPUTTXDATA(15-0)
• Input parity PPUTTXPRTY
• Input start of packet PPUTTXSOPC
• Input end of packet PPUTTXEOP
• Input word modulo PPTXMOD
• Input error PPTXERR
• Input write enable PPUTTXENB
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High Order Pointer Tracking, Retiming and Pointer Generation
PHY’s are possible
possible
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