TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 81

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

8 1 o f 2 2 6
Symbol
a. Only applies if a read access is preceded by a write access. R/W may stay high between 2 suc-
b. CS may stay low between 2 successive accesses to the same peripheral.
c. Only applies if a read access is followed by a write access. R/W may stay high between 2 suc-
d. No timing constraint between the rising edges of CS and DS are defined, since no such rela-
e. Between accesses to different peripherals
t
t
t
H3
t
t
t
SU2
SU3
t
D10
t
t
t
t
t
t
t
t
t
t
SU1
SU4
H2
cessive read accesses.
cessive read accesses.
tionship is defined in the MC68360 data sheet. CS is only latched at the beginning of an
access.
t
t
H1
D1
D2
D3
D4
D5
D6
D7
D8
D9
t
H
L
b, d
c
e
a
b
20 ns
0.4t
0.4t
-0.9t
0 ns
0 ns
0.7t
0 ns
0 ns
-
0 ns
0 ns
0 ns
4 ns
-
t
TBD
0 ns
0 ns
t
Min
-
-
-
-
-
-
-
-
20 ns
8 ns
7 ns
-
20 ns
-
TBD
12 ns
12 ns
-
-
-
Max
- Timing Characteristics -
CLK clock period
CLK clock low phase pulse width
CLK clock high phase pulse width
Setup time of A to falling edge DS
Setup time of R/W to falling edge DS
Setup time of CS to falling edge DS
Setup time of D to active edge DSACK
Hold time of A to active edge DSACK
Hold time of R/W to rising edge DS
Hold time of CS to rising edge DS
Delay from falling edge DS to DSACK driving
Delay from falling edge CLK to active edge DSACK
Delay from rising edge DS to inactive edge DSACK
Delay from DSACK going inactive to DSACK going in tristate
Delay from rising edge DS to DSACK going in tristate
DS inactive pulse width
Response latency
Delay from falling edge DS to D driving
Delay from rising edge DS to D going in tristate
CS inactive pulse width
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005