MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 120

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

ColdFire Flash Module (CFM)
6.3.4
The Flash registers are described in this subsection.
6.3.4.1
The CFMCR is used to configure and control the operation of the CFM array.
Bits 10 -5 in the CFMCR register are readable and writable with restrictions.
6-8
Address
1
2
Reset
Field
R/W
IPSBAR Offset
S = Supervisor access only. User mode accesses to supervisor only addresses have no effect and result in a
cycle termination transfer error.
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses
to these reserved address spaces and reserved register bits have no effect.
15–11
Bits
0x1D_001C
0x1D_0014
0x1D_0018
0x1D_0020
0x1D_0024
10
9
8
Register Descriptions
CFM Configuration Register (CFMCR)
15
—
Name
LOCK
PVIE
AEIE
Figure 6-4. CFM Module Configuration Register (CFMCR)
—
CFMUSTAT
Bits 31–24
CFMCMD
11
Table 6-3. CFM Register Address Map
Table 6-4. CFMCR Field Descriptions
Reserved, should be cleared.
Write lock control. The LOCK bit is always readable and is set once.
1 CFMPROT, CMFSACC, and CFMDACC register are write-locked.
0 CFMPROT, CMFSACC, and CFMDACC register are writable.
Protection violation interrupt enable. The PVIE bit is readable and writable. The
PVIE bit enables an interrupt in case the protection violation flag, PVIOL, is set.
1 An interrupt will be requested whenever the PVIOL flag is set.
0 PVIOL interrupts disabled.
Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit
enables an interrupt in case the access error flag, ACCERR, is set.
1 An interrupt will be requested whenever the ACCERR flag is set.
0 ACCERR interrupts disabled.
LOCK PVIE AEIE CBEIE CCIE KEYACC
10
Bits 23–16
9
0000_0000_0000_0000
IPSBAR + 0x1D_0000
CFMSACC
CFMDACC
Reserved
8
R/W
7
2
Bits 15–8
Reserved
Reserved
6
Description
2
2
5
Bits 7–0
4
Freescale Semiconductor
—
Access
S
S
S
S
S
1
0