MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 493

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

25.5.6
Table 25-14
25.5.7
These registers are used as acceptance masks for received frame IDs. 3 masks are defined: A global mask,
used for Rx buffers 0-13, and 2 more separate masks for buffers 14 and 15.
Mask bit = 0: The corresponding incoming ID bit is “don’t care”.
Mask bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
Note that these masks are used both for Standard and Extended ID formats. The value of mask registers
should NOT be changed while in normal operation, as locked frames which matched a MB through a mask,
may be transferred into the MB (upon release) but may no longer match.
Freescale Semiconductor
15–0
Bits
Bits
5–3
2–0
Address
Reset
Field
R/W
TIMER The free running timer counter can be read and written by the CPU. The timer starts from zero after
Name
PSEG
PSEG
Name
Free Running Timer (TIMER)
Rx Mask Registers
describes the TIMER fields.
1
2
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer segment
1 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 1 is calculated as follows:
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer segment 2
in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 2 is calculated as follows:
reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock. During a message, it increments by one for each bit
that is received or transmitted. When there is no message on the bus, it increments at the nominal bit
rate.
The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. The
captured value is written into the “time stamp” entry in a message buffer after a successful reception
or transmission of a message.
15
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
Table 25-13. CANCTRL2 Field Descriptions (continued)
Figure 25-11. Free Running Timer (TIMER)
Table 25-14. TIMER Field Descriptions
0000_0000_0000_0000
IPSBAR + 0x1C_000A
Description
Description
TIMER
R/W
0
FlexCAN
25-23