MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 330

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Fast Ethernet Controller (FEC)
17.4.15 Descriptor Individual Upper Address Register (IAUR)
IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the destination address (DA) field of receive
frames with an individual DA. This register is not reset and you must initialize it.
17.4.16 Descriptor Individual Lower Address Register (IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the DA field of receive frames with an individual
DA. This register is not reset and you must initialize it.
17-20
PAUSE_DUR
IADDR1
OPCODE
Field
31–0
31–16
Field
15–0
IPSBAR
IPSBAR
Offset:
Offset:
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
W
W
R
R
Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.
Pause Duration field used in PAUSE frames.
0x10EC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x1118
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Figure 17-15. Descriptor Individual Upper Address Register (IAUR)
Figure 17-14. Opcode/Pause Duration Register (OPD)
OPCODE
Table 17-19. IAUR Field Descriptions
Table 17-18. OPD Field Descriptions
Description
IADDR1
Description
PAUSE_DUR
8
8
7
7
Access: User read/write
Access: User read/write
6
6
Freescale Semiconductor
5
5
4
4
3
3
2
2
1
1
0
0