MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 585

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

28.8.4
When disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
When both queue 1 and queue 2 are disabled, there is no possibility of encountering wait states when
accessing CCW table and result RAM. When both queues are disabled, it is safe to change the QCLK
prescaler values.
28.8.5
Reserved mode is available for future mode definitions. When reserved mode is selected, the queue is not
active. The behavior is the same as disabled mode.
28.8.6
A single-scan queue operating mode is used to execute a single pass through a sequence of conversions
defined by a queue. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, these modes
can be selected:
In all single-scan queue operating modes, queue execution is enabled by writing the single-scan enable bit
to a 1 in the queue’s control register. The single-scan enable bits, SSE1 and SSE2, are provided for queue
1 and queue 2, respectively.
Until a queue’s single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan
enable bit may be set to a 1 during the same write cycle that selects the single-scan queue operating mode.
The single-scan enable bit can be written only to 1, but will always read 0. Once set, writing the single-scan
enable bit to 0 has no effect. Only the QADC can clear the single-scan enable bit. The completion flag,
completion interrupt, or queue status is used to determine when the queue has completed.
After the single-scan enable bit is set, a trigger event causes the QADC to begin execution with the first
CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the queue
reaches completion, the QADC resets the single-scan enable bit to 0. Writing the single-scan enable bit to
a 1 or a 0 before the queue scan is complete has no effect; however, if the queue operating mode is changed,
the new queue operating mode and the value of the single-scan enable bit are recognized immediately. The
conversion in progress is aborted, and the new queue operating mode takes effect.
In software-initiated single-scan mode, writing a 1 to the single-scan enable bit causes the QADC to
generate a trigger event internally, and queue execution begins immediately. In the other single-scan queue
operating modes, once the single-scan enable bit is written, the selected trigger event must occur before
the queue can start. The single-scan enable bit allows the entire queue to be scanned once. A trigger
overrun is captured if a trigger event occurs during queue execution in an edge-sensitive external trigger
mode or a periodic/interval timer mode.
In the interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue.
After queue execution is complete, the queue status is shown as idle. The queue can be restarted by setting
the single-scan enable bit to 1. Queue execution begins with the first CCW in the queue.
Freescale Semiconductor
•
•
•
•
Software-initiated single-scan mode
Externally triggered single-scan mode
Externally gated single-scan mode
Interval timer single-scan mode
Disabled Mode
Reserved Mode
Single-Scan Modes
Queue 2 cannot be programmed for externally gated single-scan mode.
NOTE
Queued Analog-to-Digital Converter (QADC)
28-47