MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 640

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Debug Support
The sequence is as follows:
30.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in
30-22
•
•
•
•
•
READ (LONG)
Commands transmitted to the debug module
Responses from the debug module
In cycle 1, the development system command is issued (
responds with either the low-order results of the previous command or a command complete status
of the previous command, if no results are required.
In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
In cycle 3, the development system supplies the low-order 16 address bits. The debug module
always returns a not-ready response.
At the completion of cycle 3, the debug module initiates a memory read operation. Any serial
transfers that begin during a memory access return a not-ready response.
Results are returned in the two serial transfer cycles after the memory access completes. For any
command performing a byte-sized memory read operation, the upper 8 bits of the response data are
undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is
sent to the debug module during the final transfer. If a memory or register access is terminated with
a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data.
???
Command code transmitted during this cycle
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
Results from previous command
’NOT READY’
MS ADDR
’ILLEGAL’
Sequence taken if illegal command
is received by debug module
XXX
High-order 16 bits of memory address
Figure 30-16. Command Sequence Diagram
’NOT READY’
’NOT READY’
Data used from this transfer
NEXT CMD
LS ADDR
Low-order 16 bits of memory address
NOTE
Non-serial-related
LOCATION
MEMORY
activity
READ
READ
Table
in this example). The debug module
30-17.
’NOT READY’
Sequence taken if bus error
occurs on memory access
MS RESULT
Sequence taken if operation
has not completed
High- and low-order 16 bits of result
BERR
XXX
XXX
XXX
Freescale Semiconductor
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
Command
Code
Next