MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 288

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Synchronous DRAM Controller Module
Figure 15-8
request becomes active. The request is delayed by the precharge to
SDRAM bank by the CAS bits. The
DCR[RTIM] is inserted before the next
is initiated, but does not generate an SDRAM access until T
active during the
SDRAM_CS[0] or [1]
15.2.3.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time
to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The
DRAM controller supports self-refresh with DCR[IS]. When IS is set, the
SDRAM. When IS is cleared, the
self-refresh operation.
15-16
CLKOUT
DRAMW
A[23:0]
SRAS
SCAS
shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh
REF
command, it is passed to both blocks of external SDRAM.
PALL
t
RCD
= 2
SELFX
Figure 15-8. Auto-Refresh Operation
ACTV
command is sent to the DRAM controller.
REF
REF
command is then generated and the delay required by
command is generated. In this example, the next bus cycle
RC
is finished. Because both chip selects are
t
RC
ACTV
= 6
delay programmed into the active
SELF
command is sent to the
Figure 15-9
Freescale Semiconductor
shows the
ACTV