MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 159
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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8.4.5
The software watchdog service sequence must be performed using the CWSR as a data register to prevent
a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55
followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but
any number of instructions or accesses to the CWSR can be executed between the two writes. If the CWT
has already timed out, writing to this register has no effect in negating the CWT interrupt.
illustrates the CWSR. At system reset, the contents of CWSR are uninitialized.
8.5
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic
that controls which of up to four MBus masters (M0–M3 in
The function of the arbitration logic is described in this section.
Freescale Semiconductor
5–3
2
1
0
Internal Bus Arbitration
CWTAVAL Core watchdog transfer acknowledge valid.
CWT[2:0] Core watchdog timing delay. These bits select the timeout period for the CWT. At system reset, the
Core Watchdog Service Register (CWSR)
CWTIF
CWTA
Address
Reset
CWT field is cleared signaling the minimum time-out period but the watchdog is disabled
(CWCR[CWE] = 0).
Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
Field
R/W
assertion of the CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate
a bus cycle and allow the interrupt acknowledge to occur.
Figure 8-5. Core Watchdog Service Register (CWSR)
CWT
000
001
010
011
7
Table 8-5. CWCR Field Description (continued)
2
2
2
CWT Time-Out Period
2
11
13
15
9
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
IPSBAR + 0x013
Uninitialized
CWSR[7:0]
R/W
Figure
CWT
100
101
110
111
8-6) has access to the external buses.
2
2
2
2
CWT Time-Out Period
19
23
27
31
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
System Control Module (SCM)
0
Figure 8-5
8-7
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