MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 158

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

System Control Module (SCM)
When the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, an
internal reset is asserted and CRSR[CWDR] is set. To prevent the core watchdog timer from interrupting
or resetting, the CWSR must be serviced by performing the following sequence:
Both writes must occur in order before the time-out, but any number of instructions can be executed
between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two
writes. Caution should be exercised when changing CWCR values after the software watchdog timer has
been enabled with the setting of CWCR[CWE], because it is difficult to determine the state of the core
watchdog timer while it is running. The countdown value is constantly compared with the time-out period
specified by CWCR[CWT]. The following steps must be taken to change CWT:
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer
acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At
system reset, the software watchdog timer is disabled.
8-6
1. Write 0x55 to CWSR.
2. Write 0xAA to the CWSR.
1. Disable the core watchdog timer by clearing CWCR[CWE].
2. Reset the counter by writing 0x55 and then 0xAA to CWSR.
3. Update CWCR[CWT].
4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed in step
Bits
7
6
3.
Name
CWRI
CWE
Address
Reset
Field
R/W
Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
Core watchdog reset/interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for
1 Reserved; do not use.
the CWT is programmed in the interrupt control register 8 (ICR8) of INTC0.
CWE
Figure 8-4. Core Watchdog Control Register (CWCR)
7
CWRI
6
Table 8-5. CWCR Field Description
5
CWT[2:0]
IPSBAR + 0x011
0000_0000
R/W
Description
3
CWTA
2
CWTAVAL
1
CWTIC
Freescale Semiconductor
0