MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 322

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Fast Ethernet Controller (FEC)
17.4.5
The TDAR is a command register which the user writes to indicate the transmit descriptor ring is updated
(transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).
When the register is written, the TDAR bit is set. This value is independent of the data actually written by
the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided
ECR[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC
clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again, signifying
additional descriptors are placed into the transmit descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.
17.4.6
ECR is a read/write user register, though hardware may alter fields in this register as well. The ECR
enables/disables the FEC.
17-12
31–25
RDAR
31–25
TDAR
Field
23–0
Field
23–0
24
24
IPSBAR
Offset:
Reset 0 0 0 0 0 0 0
Reserved, must be cleared.
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, must be cleared.
W
Reserved, must be cleared.
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, must be cleared.
R 0 0 0 0 0 0 0
Transmit Descriptor Active Register (TDAR)
Ethernet Control Register (ECR)
0x1014
31 30 29 28 27 26 25
Figure 17-5. Transmit Descriptor Active Register (TDAR)
TDAR
24
0
Table 17-7. RDAR Field Descriptions
Table 17-8. TDAR Field Descriptions
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
Description
8
7
Access: User read/write
6
Freescale Semiconductor
5
4
3
2
1
0