MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 492

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

FlexCAN
25.5.4
Table 25-12
25.5.5
Table 25-13
25-22
Bits
7–6
Bits
7–0
Address
Address
Reset
Reset
Field
Field
R/W
R/W
Name
Prescaler Divide Register (PRESDIV)
FlexCAN Control Register 2 (CANCTRL2)
PRES_DIV Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency and
RJW
describes the PRESDIV fields.
describes the CANCTRL2 fields.
Name
Resynchronization jump width. The RJW field defines the maximum number of time quanta a bit time
may be changed during resynchronization. The valid programmed values are 0 through 3.
The resynchronization jump width is calculated as follows:
7
7
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency
as the system clock. The valid programmed values are 0 through 255. See
Timing” for more information.
RJW
Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)
Figure 25-9. Prescaler Divide Register (PRESDIV)
6
Table 25-13. CANCTRL2 Field Descriptions
Table 25-12. PRESDIV Field Descriptions
5
IPSBAR + 0x1C_0008
IPSBAR + 0x1C_0009
S-clock
PSEG1
PRES_DIV
0000_0000
0000_0000
Description
R/W
Description
R/W
=
-------------------------------------------- -
2 PRESDIV + 1
(
3
f sys
)
2
PSEG2
Section 25.4.8, “Bit
Freescale Semiconductor
0
0