MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 141

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

7.3
The functions and characteristics of the low-power modes, and how each module is affected by, or affects,
these modes are discussed in this section.
7.3.1
The system enters a low-power mode by executing a STOP instruction. Which mode the device actually
enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD]. Entry into any of
these modes idles the CPU with no cycles active, powers down the system and stops all internal clocks
appropriately. During stop mode, the system clock is stopped low.
For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued.
A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of
any of these conditions:
The latter method of exiting from low-power mode, by a valid and enabled interrupt request, requires
several things:
7.3.1.1
Run mode is the normal system operating mode. Current consumption in this mode is related directly to
the system clock frequency.
Freescale Semiconductor
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STPMD[1:0]
Any type of reset
Any valid, enabled interrupt request
An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field
of the LPICR
An interrupt request whose priority higher than the value programmed in the interrupt priority
mask (I) field of the core’s status register
An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask
register
An interrupt request which has been enabled at the module of the interrupt’s origin
00
01
10
11
Functional Description
Low-Power Modes
Run Mode
If LPCR[LPMD] is cleared, then the device stops executing code upon issue
of a STOP instruction. However, no clocks are disabled.
System Clocks
Disabled
Disabled
Disabled
Disabled
Table 7-6. PLL/CLKOUT Stop Mode Operation
CLKOUT
Disabled
Disabled
Disabled
Enabled
Operation During Stop Mode
NOTE
Disabled
Disabled
Enabled
Enabled
PLL
Disabled
Enabled
Enabled
Enabled
OSC
Low-Power Option
Power Management
Enabled
Enabled
Enabled
PMM
7-5