CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 104

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
The MSE bit in the Command Register must be set high to enable the MultiSearch feature. The same with the Enhanced Mode
(EMODE) bit. The following is the sequence of operation for a single mixed-width Search command (also refer to Subsection 6.2,
“Command Bus Parameters,” on page 50).
Notes.
The latency of the MultiSearch from command to SRAM access cycle is 5 for a configuration of up to eight devices (TLSZ = 01
(binary)). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-8.
6.6
The device contains sixteen pairs of Comparand (CMPR) registers that store the search key as the device executes searches.
On a Search miss, signalled to the ASIC through the SSV and SSF signals (SSV = 1 (binary), SSF = 0 (binary)), the host ASIC
can apply the Learn command to learn the entry from a CMPR register to the next-free location. However, it is recommended that
the host ASIC first check the FULL signal, to determine if the device is full. If the device is not full, and the Search was a miss, a
Learn can be applied. If the device is already full, and the Learn is issued, the operation will be suppressed. The Learn Command
latency is calculated from the first cycle after the learn is issued. Irrespective of the width of the learn, the latency of the SADR
bus is calculated to be 5+TLSZ after the first cycle. This calculation is shown in Table 6-14, which shows latency values for
different learn widths after each of the commands are issued.
1. For 72-bit leading + 72-bit trailing Multisearches, the host ASIC can supply different 72-bit data on DQ[71:0] during both cycles
2. For all other Multisearch commands that contain a 72-bit trailing search, you must pay special attention to which part of the
3. For all other Multisearches, the N-bit search key used for the N-bit trailing search is simply the last N-bits presented on the
4. GMR and CPR selection also deserve special attention, please see Section 5.1.2.4 for details.
5. A matching entry from each array that satisfies the Soft Priority and Mini-Key scheme will be the winning entries, and their
6. Reading CMPR registers after Multisearches: You can only do this if your leading and trailing searches are of same width.
7. Learning from CMPR is only supported if your leading and trailing searches are of same width.
• Cycle A:
• Cycle B:
A and B to be compared with the tables in array 0 and 1 of the data array. The even and odd pairs of GMRs selected for the
comparison need not be programmed with the same value.
entire search key is used for the 72-bit trailing search. An example of this situation is illustrated in M-search 2 and M-search
3 in Figure 6-7. M-search 2 is a 144-bit leading search on Array 0 plus a 72-bit trailing search on Array 1. Notice that the Y2
portion of the entire key is used during the 72-bit search. A different behavior is observed for a leading search in Array 1 instead
of Array 0. M-search 3 is a 288bit leading search on Array 1 plus a 72-bit trailing search on Array 0. In this example, Z3 is
used as the 72-bit key for the trailing 72-bit search. The difference between M-search 2 and M-search 3 is the trailing 72-bit
search (Array 0 and Array 1 respectively). This behavior is summarized as follow:
DQ bus when the Multisearch command is issued.
location addresses La and Lb will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM
PIO Access,” on page 113), N = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A.
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). The CMD[2]
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
•
•
72-bit trailing search on Array 0: Data on DQ during the last Cycle A of the entire Search command will be used as search key
72-bit trailing search on Array 1: Data on DQ during the last Cycle B of the entire Search command will be used as search key
and CMD[9] signals must be driven to logic 0 for the 72-bit search, but for 144-bit search, CMD[9] = 1 and CMD [2] = 0.
For 288-bit search, CMD[9] is don’t care, whereas CMD[2] = 1 for the first “A” cycle and 0 for the last “A” cycle.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[7:6]
signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512A, SADR[23:22] for
CYNSE10256A, SADR[22:21] for CYNSE10128A by this device if it has a hit. CMD[8] must be set high for MultiSearch
operation. Note, CMD[8] must be driven low for all Cycle A’s of Single Search operations if MSE = 1 in CMD Register.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the search key presented on the DQ
bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the
address of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
Learn Command
CONFIDENTIAL
CYNSE10512A
CYNSE10256A
CYNSE10128A
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