CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 65

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
The following is the sequence of operation for a single 72-bit Search command (also refer to Subsection 6.2, “Command Bus
Parameters,” on page 50).
• Cycle A:
• Cycle B:
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A
CFG are all zeroes for Non-Enhanced Mode,
NES = 00 (binary) in each block for Enhanced Mode.
HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary).
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10”. The CMD[2] and
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data to be compared.
CMD[9] signals must be driven to logic 0 for this 72-bit search. {CMD[10],CMD[5:3]} signals must be driven with the index
to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on
SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A by this device if it has
a hit. If Enhanced Mode and MultiSearch Enable bits are both set to 1in the Command Resister, CMD[8] has to be set to
0 for Single Searches. For 288-bit and 576-bit Single Searches, all Cycle A CMD[8] bits have to be set to 0’s.
must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the DQ bus
during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address
of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
SADR[M:0]
CMD[10:2]
|(LHI[6:0])
CMD[1:0]
LHO[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
Figure 6-13. Timing Diagram for 72-bit Search Device Number 7 (Last Device)
SSV
SSF
DQ
0
0
0
0
0
1
0
0
CONFIDENTIAL
cycle
Search1
A B A B A B A B
1
10
W
cycle
Search2
2
10
X
cycle
Search3
3
10
Y
cycle
4
Search4
10
Z
cycle
5
cycle
6
1
cycle
7
z
z
Search1
(Miss on
this device)
z
z
cycle
1
8
Search2
(Miss on
this device)
cycle
9
Addr
z
z
Z
Search3
(Local
winner but
not global
winner)
cycle
10
CYNSE10512A
CYNSE10256A
CYNSE10128A
Search4
(Global
winner)
0
0
0
0
1
1
1
0
0
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