CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 53

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.3.2
The burst Read operation lasts 4 + 2n CLK1X cycles, where n is the number of the burst length as specified by the BLEN field
of the RBURREG. The BLEN field is automatically decremented after each Read of the burst, so the register must be reinitialized
before another burst Read is issued. Instead of the address provided by the user, the address in the INDEX field of the RBURREG
is used and incremented each cycle.
Figure 6-2 illustrates the timing diagram for the burst Read of the data or mask array.
Burst Read operation sequence:
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of RBURREG are complete.
On the last data transfer, the Ayama 10000A drives the EOT signal HIGH.
Cycle (4 + 2n): The selected device drives the DQ[71:0] to a three-state condition, and drives ACK and EOT signals LOW.
At the termination of cycle (4 + 2n), the selected device floats ACK and EOT to a three-state condition. The burst Read operation
is complete and the next operation can begin.
6.3.3
Data output of the Read Parity command should be ignored. Read Parity is a blocking operation only on cycles equivalent to a
regular Read operation, ignoring the fact that the parity status signal (PARERR) is valid TLSZ cycles later.
6.4
The Write command can be issued to write to the data array, mask array, NSE-associated SRAMs or internal registers. The Write
can be a single or burst Write (Table 6-6). Burst Write can only be issued for accesses to the data or mask array locations. SRAM
Write operation is covered in Section 6.7.4 to Section 6.7.6. The Write command is also used to issue the Parallel Write command.
When a Write command is issued, a GMR needs to be specified. This GMR will be used to mask out bits written to the data or
mask array. The upper 72-bit and lower 72-bit of the selected GMR MUST be the exact copy of each other.
Note that when Parity feature is enabled masks will be ignored and all bits will be written as presented in the DQ bus.
Write is a blocking operation and must be completed before the next operation can be issued.
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the start address is
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the address location on the DQ[71:0] bus and drives the ACK signal
provided in the RBURREG register. The host ASIC selects the Ayama 10000A device where ID[4:0] matches the DQ[25:21]
lines. If DQ[25:21] = 11111, the host ASIC selects the Ayama 10000A device with the LDEV bit set.
HIGH.
Burst Read
Read Parity
Write Command
CMD[10:2]
CMD[1:0]
CMDV
CLK2X
PHS_L
ACK
EOT
DQ
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
cycle
Read
A B
1
CONFIDENTIAL
cycle
2
cycle
3
cycle
4
0
cycle
Data0
5
cycle
6
0
cycle
Data1
7
cycle
8
0
cycle
Data2
9
cycle
10
0
cycle
11
Data3
cycle
12
CYNSE10512A
CYNSE10256A
CYNSE10128A
Page 53 of 145