CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 84

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
The following is the sequence of operation for a single 576-bit Search command (also refer to Subsection 6.2, “Command Bus
Parameters,” on page 50).
Note. For 576-bit searches, the host ASIC must supply individual 72-bit data on DQ[71:0] during cycles A and B. Also, four
individual pairs of GMR and CMPR registers may be involved in the comparison.
The logical 576-bit Search operation is shown in Figure 6-30. The entire table of 576-bit entries (eight devices) is compared to a
576-bit word K that is presented on the DQ bus in eight cycles using the GMR and local mask bits. The GMR is the 576-bit word
specified by four pairs of GMRs selected by GMR indices in each of the eight devices. The 576-bit word K (presented on the DQ
bus in all eight cycles of the command) is also stored in both even and odd comparand register pairs (selected by the comparand
register index in command cycle B) in each of the eight devices. The word K is compared with each entry in the table, starting at
location 0 (decimal). A matching entry that satisfies the Soft Priority and Mini-Key scheme will be the winning entry, and its location
address L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113),
N = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. The global winning device will drive the bus in a specific
cycle. On a global miss cycle, the device with LRAM = 1 (binary) (default driving device for the SRAM bus) and LDEV = 1 (binary)
(default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at one-eighth the rate of the frequency of CLK2X for 576-bit
searches in ×576-configured tables. The latency of the Search from command to SRAM access cycle is 5 for up to eight devices
in the table (TLSZ = 01 (binary)). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-8.
• Cycle A:
• Cycle B:
Will be same in each of the eight
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). CMD[2] must
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with 72-bit data (which is part of the 576-bit data) to be
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data (which is part of the 576-bit data) to be compared.
Comparand Register (Odd)
Comparand Register (Even)
be driven to logic 1 for the first three A-cycles and then driven to logic 0 for the final A-cycle for 576-bit search.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. Each of the
four A-cycles provide a GMR index to mask 144 bits of the data to be compared (each A-cycle provide a pair of GMR, which
is 144 bits, four A-cycles will result in a total of 576 bits of GMR). CMD[8:6] signals must be driven with the same bits that
will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A by
this device if it has a hit. If Enhanced Mode and MultiSearch Enable bits are both set to 1in the Command Resister, CMD[8]
has to be set to 0 for Single Searches. For 288-bit and 576-bit Single Searches, all Cycle A CMD[8] bits have to be set to
0’s. CMD[9] is don’t care for this cycle.
compared.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the
DQ bus during cycles A and B. Each of the four B-cycles provide an index for a pair of comparand register. CMD[8:6] signals
must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag (see
page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
71
devices
Must be same in each
of the eight devices
K
K
0
Location
address
CONFIDENTIAL
Figure 6-30. ×576 Table with Eight Devices
GMR
0
1
2
3
N
L
K
575
575
(576-bit configuration)
N = 262143 for CYNSE10512A
131071 for CYNSE10256A
65535 for CYNSE10128A
CYNSE10512A
CYNSE10256A
CYNSE10128A
0
0
(First matching
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