CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 122

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
At the end of cycle 3, a new command can begin. Write is a pipelined operation, but the Write cycle appears at the SRAM bus
with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the Ayama 10000A device.
• Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the Ayama 10000A device.
address with DQ[20:19] set to 10 to select the SRAM address.
Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported.
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
SSF
TLSZ = 01 (binary), HLAT = XXX, LRAM = 0 (binary), LDEV = 0 (binary)
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A
DQ
Figure 6-65. SRAM Write of Device #0 in a Block of Eight Devices
z
z
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CONFIDENTIAL
Address
cycle
Write
1
A B
01
cycle
2
x
cycle
3
x
cycle
4
cycle
5
cycle
6
cycle
7
Address
cycle
8
0
0
0
cycle
9
z
cycle
10
CYNSE10512A
CYNSE10256A
CYNSE10128A
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z
z
z
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