CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 112

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Table 6-15. SRAM Write Cycle Latency from Second Cycle of Learn Instruction
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
At the end of cycle 2, a new instruction can begin. SRAM Write latency is the same as the Search to the SRAM Read cycle. It is
measured from the second cycle of the Learn instruction.
TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary).
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1 (binary). The CMD[5:2] field specifies
• Cycle 1B: The host ASIC continues to drive CMDV to 1 (binary), CMD[1:0] to 11 (binary), and CMD[5:2] with the comparand
• Cycle 2: The host ASIC drives CMDV to 0.
the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a Learn in a
72-bit-configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that
will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A in the
SRAM Write cycle.
pair index. CMD[6] must be set to 0 if the Learn is being performed on a 72-bit-configured table, and to 1 if the Learn is being
performed on a 144-bit-configured table.
1–31 (TLSZ = 10 (binary))
1–8 (TLSZ = 01 (binary))
Number of Devices
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
ALE_L
OE_L
Figure 6-55. Timing Diagram of Learn on Device Number 7 (TLSZ = 01 (binary))
WE_L
CE_L
SSV
SSF
DQ
0
0
0
z
z
1
1
1
CONFIDENTIAL
Comp1
cycle
Learn1
1A 1B
1
X
cycle
2
X
X
X
X
cycle
Comp2
Learn2
3
X
cycle
4
X
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A
X
X
X
cycle
5
z
cycle
1
6
Latency in CLK Cycles
cycle
7
z
z
z
z
cycle
8
1
1
1
5
6
cycle
9
z
z
z
z
cycle
10
z
1
1
1
0
CYNSE10512A
CYNSE10256A
CYNSE10128A
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