CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 13

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Table 3-1. Ayama™ 10000A Signal Description (continued)
DQ[71:0]
PAR[1:0]
ACK
EOT
SSF
SSV
MULTI_HIT
FULL
HIGH_SPEED1
HIGH_SPEED2
HIGH_SPEEDI_L
SRAM Interface (LVCMOS or HSTL I/II)
SADR[M:0]
CE_L
WE_L
OE_L
ALE_L
Notes:
3.
4.
Require an external pull-down resistor such as 47K
recommended.
These signals will output at the rising edge of CLK2X (both rising and falling edges of CLK1X) in a MultiSearch operation.
[4]
[4]
[3]
[3]
Parameter
[4]
[4]
[4]
[4]
[4]
[4]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ_SRAM
DDQ_SRAM
DDQ_SRAM
DDQ_SRAM
DDQ_SRAM
Type
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
Supply
I/O,
I/O
O,
T,
T,
T,
T,
T,
T,
T,
T,
T,
T,
I,
I,
I,
[1]
,
Address/Data Bus. This signal carries the following information:
Search operation: Compare Data (Search Key)
SRAM PIO operations: SRAM Address
Other operations to Register, Data, and Mask Array regions: Address and Data
Parity Bus. These signals contain the even parity values for the DQ bus. On the Read return
data, the NSE generates the parity bits. On all other operations these bits are externally
driven. Bit [0] is the parity for all even DQ signals. Bit[1] is the parity for all odd DQ signals.
Read Acknowledge. This signal indicates that valid data is available on the DQ bus during
register, data, and mask array Read operations, or that the data is available on the SRAM
data bus during SRAM Read operations.
End of Transfer. This signal indicates the end of burst transfer to the data or mask array
during Read or Write burst operations.
Search Successful Flag. When asserted, this signal indicates that the device is the global
winner in a Search operation.
Search Successful Flag Valid. When asserted, it indicates valid SSF value. In Enhanced
mode, this signal also indicates valid FULL and MULTI_HIT values.
Multiple Hit Flag. In a Search operation, this signal indicates that there are multiple entries
in the array or in the selected blocks that match the Search key when it is set to 1. In a Learn
operation, it indicates that there are multiple free entries.
In Non-Enhanced mode, it becomes valid four CLK1X cycles after the command is issued.
In Enhanced mode, it becomes valid when SSV is 1.
Full Flag. When High, it indicates that the table in the array or in the selected blocks
(Enhanced mode) is full.
In the Non-Enhanced mode, it becomes valid four CLK1X cycles after the command is
issued.
In the Enhanced mode, it becomes valid when SSV is 1. The FULL flag is only asserted
when there is a Search Miss on a full device. A Search Hit on a full device would not assert
the FULL flag. It is not driven when a Write or a Learn takes place.
High Speed 1. This signal must be pulled High (V
CLK2X frequency greater than or equal to 166 MHz but less than 200 MHz.
High Speed 2. This signal must be pulled High (V
CLK2X frequency greater than or equal to 200 MHz, with High Speed 1 tied Low.
High Speed I_L. When High (V
Highspeed feature is enabled and is configurable through HARDWARE register.
SRAM Address. This bus contains address lines to access off-chip SRAMs that contain
associative data. In a cascaded system of multiple Ayama 10000A NSEs, each corre-
sponding SADR bit from all cascaded devices must be tied together.
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A.
SRAM Chip Enable. This is the chip enable (CE) control for external SRAMs. In a cascaded
system of multiple Ayama 10000A NSEs, CE_L of all cascaded devices must be tied
together. This signal is then driven by only one of the devices that acts as a master device.
SRAM Write Enable. This is the Write enable control for external SRAMs. In a cascaded
system of multiple Ayama 10000A NSEs, WE_L of all cascaded devices must be tied
together. This signal is then driven by only one of the devices.
SRAM Output Enable. This is the output enable (OE) control for external SRAMs. Only the
last device drives this signal (the device that has the LRAM bit set).
Address Latch Enable. When this signal is Low, the addresses are valid on the SRAM
address bus. In a cascaded system of multiple Ayama 10000As, the ALE_L of all cascaded
devices must be tied together. This signal is then driven by only one of the devices.
CONFIDENTIAL
Ω
or 100K
Ω
. For terminated lines, a 70-ohm pull-down and 165-ohm pull-up resistor combination is
DDQ_ASIC
Description
), High-speed feature disabled. When Low,
DDQ_ASIC
DDQ_ASIC
) when the device operates at
) when the device operates at
CYNSE10512A
CYNSE10256A
CYNSE10128A
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