CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 119

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.7.4
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the appearance of the address on the SRAM bus is the same as Search instruction latency, and will depend
on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 01 (binary), HLAT = 000 (binary), LRAM
= 1 (binary), and LDEV = 1 (binary). Figure 6-63 shows the timing diagram. For the following description, the selected device
refers to the only device in the table because it is the only device that will be accessed.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; the Write cycle appears at the SRAM bus,
however, with the same latency as the Search instruction, as measured from the second cycle of the Write command.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
• Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported.
• Cycle 2 and cycle 3: wait states. Data not used by NSE.
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for
CYNSE10128A on CMD[8:6] in this cycle.
address with DQ[20:19] set to 10 to select the SRAM address.
SRAM Write with a Table of One Device
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
SSF
DQ
TLSZ = 10 (binary), HLAT = 010 (binary), LRAM = 1 (binary), LDEV = 1 (binary)
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A
Figure 6-62. SRAM Read of Device #0 in a Bank of 31 Devices
0
1
1
z
0
0
1
CONFIDENTIAL
cycle
Address
Read
1
A B
00
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
z
z
z
z
cycle
8
1
1
1
cycle
9
cycle
10
CYNSE10512A
CYNSE10256A
CYNSE10128A
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