CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 3

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.0 OPERATIONS AND TIMING DIAGRAMS .....................................................................................50
7.0 JTAG (IEEE 1149.1) .....................................................................................................................126
8.0 POWER CONSUMPTION .............................................................................................................127
9.0 ELECTRICAL SPECIFICATIONS ................................................................................................128
10.0 AC TIMING PARAMETERS, WAVEFORMS AND TEST CONDITIONS ...................................129
11.0 PIN ASSIGNMENT AND PINOUT DIAGRAM ............................................................................136
12.0 ORDERING INFORMATION ......................................................................................................142
13.0 PACKAGE DIAGRAM ................................................................................................................142
6.1 Command Encoding ..................................................................................................................50
6.2 Command Bus Parameters .......................................................................................................50
6.3 Read Command ........................................................................................................................52
6.4 Write Command ........................................................................................................................53
6.5 Search Command .....................................................................................................................56
6.6 Learn Command .....................................................................................................................104
6.7 SRAM PIO Access ..................................................................................................................112
6.8 Timing Sequences for Back-to-Back Operations ....................................................................124
6.9 Full Signal Timing Diagram .....................................................................................................125
9.1 Maximum Ratings
10.1 AC Timing Parameters and Waveforms with CLK2X ............................................................129
10.2 AC Timing Parameters and Waveforms with CLK1X ............................................................131
10.3 AC Test Conditions and Output Loads ..................................................................................134
6.2.1 Extended Address (EADR) ..............................................................................................................50
6.2.2 Enhanced Mode and Non-Enhanced Mode Parameters .................................................................50
6.3.1 Single Read .....................................................................................................................................52
6.3.2 Burst Read ......................................................................................................................................53
6.3.3 Read Parity ......................................................................................................................................53
6.4.1 Single Write .....................................................................................................................................54
6.4.2 Burst Write .......................................................................................................................................54
6.4.3 Parallel Write ...................................................................................................................................55
6.5.1 Mixed-size Single Searches with One Device on Tables Configured with Different Widths ...........57
6.5.2 Mixed-size Multi Searches with One Device on Tables Configured with Different Widths ..............59
6.5.3 72-bit Single Search for 1 device or cascade up to eight devices ...................................................61
6.5.4 144-bit Single Search for Cascade Up to 31 Devices .....................................................................67
6.5.5 576-bit Single Search for One Device or Cascade up to Eight Devices ..........................................80
6.5.6 Mixed-size Single Searches with 31 Devices on Tables Configured with Different Widths ............85
6.5.7 Mixed-size Multi Searches with 8 Devices on Tables Configured with Different Widths .................97
6.6.1 Non-Enhanced Mode ....................................................................................................................105
6.6.2 Enhanced Mode ............................................................................................................................105
6.6.3 Learn Operation on Depth-Cascaded Table .................................................................................108
6.7.1 SRAM Read with a Table of One Device ......................................................................................112
6.7.2 SRAM Read with a Table of up to Eight Devices ..........................................................................113
6.7.3 SRAM Read with a Table of up to 31 Devices ..............................................................................116
6.7.4 SRAM Write with a Table of One Device ......................................................................................118
6.7.5 SRAM Write with a Table of up to Eight Devices ..........................................................................120
6.7.6 SRAM Write with Table(s) Consisting of up to 31 Devices ...........................................................122
10.3.1 HSTL I/II ......................................................................................................................................134
10.3.2 LVCMOS 2.5V/1.8V ....................................................................................................................135
(Above which the useful life may be impaired. For user guidelines, not tested.) ................. 128
CONFIDENTIAL
TABLE OF CONTENTS
(continued)
CYNSE10512A
CYNSE10256A
CYNSE10128A
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