CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 66

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
even and odd pairs of GMRs selected for the comparison must be programmed with the same value.
The logical 72-bit Search operation is shown in Figure 6-14. The entire table of 72-bit entries (eight devices) is compared to a
72-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and local mask bits. The effective
GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs, in each of the eight devices, and selected
by the GMR Index in the command’s cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command)
is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle B) in
each of the eight devices. In the ×72 configuration, only the even comparand register can subsequently be used by the Learn
command in one of the devices (the first non-full device only). The word K (presented on the DQ bus in both cycles A and B of
the command) is compared with each entry in the table, starting at location 0. A matching entry that satisfies the Soft Priority and
Mini-Key scheme (for Enhanced Mode) will be the winning entry, and its location address L will be driven as part of the SRAM
address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113), N = 25 for CYNSE10512A, 24 for
CYNSE10256A, 23 for CYNSE10128A. The global winning device will drive the bus in a specific cycle. On a global miss cycle,
the device with LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV
signals) will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit
searches in ×72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command
cycle (two CLK2X cycles) is shown in Table 6-7.
The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and
SSF also shift further to the right for different values of HLAT, as specified in Table 6-8.
Must be same in each of the eight
Will be same in each of the eight
Comparand Register (Odd)
Comparand Register (Even)
71
devices
devices
K
K
CONFIDENTIAL
Figure 6-14. ×72 Table with Eight Devices
0
Location
address
0
1
2
3
L
N
71
71
(72-bit configuration)
GMR
K
0
0
(First matching entry)
N = 2097151 for CYNSE10512A
1048575 for CYNSE10256A
524287 for CYNSE10128A
CYNSE10512A
CYNSE10256A
CYNSE10128A
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