CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 7

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Table 3-1. Ayama™ 10000A Signal Description ...................................................................................12
Table 4-1. Bit Position Match ................................................................................................................16
Table 5-1. Summary of Non-Enhanced and Enhanced Mode Features and Functions Differences ....17
Table 5-2. Summary of Supported Trailing Searches ...........................................................................22
Table 5-3. GMR and CPR Selection When Leading Search is in Array 0 .............................................22
Table 5-4. GMR and CPR Selection when Leading Search is in Array 1 .............................................23
Table 5-5. Address Spaces for Array 0 and Array 1 .............................................................................23
Table 5-6. List of Internal Registers ......................................................................................................25
Table 5-7. Search Successful Register Description ..............................................................................28
Table 5-8. Command Register Description ...........................................................................................28
Table 5-9. Information Register Description ..........................................................................................30
Table 5-10. Read Burst Register Description ........................................................................................30
Table 5-11. Write Burst Register Description ........................................................................................31
Table 5-12. NFA Register Description ..................................................................................................31
Table 5-13. Configuration Register Description ....................................................................................32
Table 5-14. Hardware Register Description ..........................................................................................33
Table 5-15. Parity Control Register Description ....................................................................................34
Table 5-16. Control Register .................................................................................................................35
Table 5-17. Search Result Register ......................................................................................................36
Table 5-18. SRR’s INDEX Composition Based on STATUS ................................................................36
Table 5-19. Block Mini-Key Register Description ..................................................................................37
Table 5-20. Block Priority Register Description .....................................................................................38
Table 5-21. Block Parity Register Description .......................................................................................39
Table 5-22. Block NFA Register Description .........................................................................................39
Table 5-23. Block Priority Register Alias for Priority #0 Fields ..............................................................41
Table 5-24. Block Priority Register Alias for Priority #1 Fields ..............................................................41
Table 5-25. Block Priority Register Alias for Priority #2 Fields ..............................................................41
Table 5-26. Block Priority Register Alias for Priority #3 Fields ..............................................................41
Table 5-27. Pipeline Stages and Maximum Operating Speed ..............................................................43
Table 5-28. Data Array, Mask Array and External SRAM Address Space Encoding ............................44
Table 5-29. SRAM Address Generation ................................................................................................44
Table 5-30. Internal Register Address Space Encoding .......................................................................45
Table 5-31. Cascadability of Operations and Features .........................................................................45
Table 6-1. Command Codes .................................................................................................................50
Table 6-2. Non-Enhanced Mode (EMODE = 0) ....................................................................................51
Table 6-3. Enhanced Mode (EMODE = 1) with MultiSearch Disabled (MSE = 0) ................................51
Table 6-4. Enhanced Mode (EMODE = 1) with MultiSearch Enabled (MSE = 1) .................................51
Table 6-5. Single/Burst Read Command Parameters ...........................................................................52
Table 6-6. Single/Burst Write Command Parameters ...........................................................................54
Table 6-7. TLSZ[1:0] Description ..........................................................................................................56
Table 6-8. Shift of SSF and SSV from SADR .......................................................................................59
Table 6-9. Hit/Miss Assumptions ...........................................................................................................63
Table 6-10. Hit/Miss Assumptions .........................................................................................................67
Table 6-11. Hit/Miss Assumptions .........................................................................................................80
Table 6-12. Hit/Miss Assumptions .........................................................................................................85
Table 6-13. Hit/Miss Assumptions in MultiSearchMode ........................................................................99
Table 6-14. Latency of SADR for different learn widths .......................................................................106
Table 6-14. SRAM Write Cycle Latency from Second Cycle of Learn Instruction ..............................112
Table 6-15. Required Idle Cycles Between Commands .....................................................................125
CONFIDENTIAL
LIST OF TABLES
CYNSE10512A
CYNSE10256A
CYNSE10128A
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