CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 54

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Table 6-6. Single/Burst Write Command Parameters
6.4.1
A single Write operation lasts 3 cycles (CLK1X) as illustrated in Figure 6-3.
Write operation sequence:
At the termination of cycle 3, another operation can begin.
6.4.2
The burst Write operation lasts 2 + n CLK1X cycles, where n is the number of the burst length as specified by the BLEN field of
the WBURREG. The BLEN field is automatically decremented after each Write of the burst, so the register must be re-initialized
before another burst Write is issued. Instead of the address provided by the user, the address in the INDEX field of the WBURREG
is used and incremented each cycle.
CMD Parameter
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the target address
• Cycle 1B:The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the address
• Cycle 2: The host ASIC drives DQ[71:0] with the data to be written to the data array, mask array, or register location of the
• Cycle 3: Idle cycle. DQ bus should be driven to 0.
supplied on the DQ bus. The host ASIC also supplies the GMR index to mask the Write to the data or mask array location on
{CMD[10], CMD[5:3]}. For SRAM WRITEs, the host ASIC must supply the SADR[25:23] for CYNSE10512A, SADR[24:22] for
CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6]. The host ASIC sets CMD[9] to 0 for a normal Write.
supplied on the DQ bus. The host ASIC continues to supply the GMR index to mask the Write to the data or mask array
locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects
all the devices when DQ[25:21] = 11111.
selected device.
CMD[2]
0
1
Single Write
Burst Write
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
Write Command
CMDV
Single Write
Burst Write
DQ
cycle 0
Writes a single location of the data array, mask array, NSE-associated SRAM or internal
registers. All access information is applied on the DQ bus.
Writes a block of locations to the data or mask array as a burst. WBURREG specifies the
starting address and the length of the data transfer from the data or mask array; it also
auto-increments the address for each access. All other access information is applied on
the DQ bus.
CONFIDENTIAL
Figure 6-3. Single Write Cycle Timing
A
cycle 1
Address
Write
B
cycle 2
Data
Description
cycle 3
0
cycle 4
CYNSE10512A
CYNSE10256A
CYNSE10128A
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