CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 114

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.7.2
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameter:
TLSZ = 01 (binary). Figure 6-57 diagrams a block of eight devices. The following assumes that SRAM access is successfully
achieved through Ayama 10000A device number 0. Figure 6-58 and Figure 6-59 show timing diagrams for device number 0 and
device number 7, respectively.
At the end of cycle 7, the selected device floats ACK in a three-state condition. A new command can begin.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0], using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0].
• Cycle 5: The selected device continues to drive DQ[71:0] and drives ACK from High-Z to LOW.
• Cycle 6: The selected device drives the Read address on SADR[N:0] lines (N = 25 for CYNSE10512A, 24 for CYNSE10256A,
• Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ bus in a three-state condition. It continues to drive ACK
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A,
SADR[23:21] for CYNSE10128A on CMD[8:6].
address, with DQ[20:19] set to 10, to select the SRAM address.
23 for CYNSE10128A) and drives ACK HIGH, CE_L LOW, WE_L HIGH, and ALE_L LOW.
LOW.
SRAM Read with a Table of up to Eight Devices
TLSZ = 01 (binary), HLAT = 000 (binary), LRAM = 1 (binary), LDEV = 1 (binary)
CMD[10:2]
CMD[1:0]
PHS_L
CLK2X
CMDV
ALE_L
SADR
WE_L
OE_L
CE_L
ACK
SSV
SSF
DQ
z
0
1
1
1
0
0
z
CONFIDENTIAL
cycle
Address
1
A
Read
Figure 6-56. SRAM Read Access
B
cycle
2
z
cycle
3
cycle
4
cycle
DQ driven by Ayama 10000A
5
0
Address
z
cycle
0
0
1
6
CYNSE10512A
CYNSE10256A
CYNSE10128A
1
1
z
cycle
7
0
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z